Tag Archives: reference designs

CAST Debuts H.264 Video Over IP – HD Encoder Subsystem

CAST H.264 Video Over IP - HD Encoder Subsystem

CAST announced the H.264 Video Over IP – HD Encoder Subsystem. The reusable subsystem makes it easier to build video streaming into mobile and other products. Reference designs for the streaming subsystem are available now for the Altera Stratix IV and Arria V families, and the Xilinx Kintex-7 line. These include the CAST and other essential IP cores implemented in an FPGA, plus the necessary interfaces, memory, drivers, and software.

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Lattice Semiconductor Announces Four Reference Designs for MachXO2 PLD

MachXO2 EFB Block Diagram

Lattice Semiconductor released four new reference designs for their low cost, low power MachXO2 family of programmable logic devices (PLDs). Lattice’s entire portfolio of reference designs optimized for the MachXO2 family can be downloaded at no cost from the Lattice website. Five new demonstration designs and three updated application notes focused on the embedded, Flash memory-based EFB are also now available.

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Xilinx Targets 3D and 4K2K Displays with Reference Designs and ACDC Baseboard

Xilinx introduced reference designs and a development baseboard for speeding the development of next-generation, 3D and 4K2K display technologies. The 4K2K Mosaic and HDTV-to-4K2K up-converter targeted reference designs are based on the new 28nm Kintex-7 Field Programmable Gate Array (FPGA). The new ACDC (Acquisition, Contribution, Distribution and Consumption) 1.0 Baseboard also uses Kintex-7 FPGA devices. The targeted reference designs and ACDC 1.0 Baseboard with the Kintex-7 FPGA will be available in Q2 2012.

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Actel SmartFusion Motor Control Development Kit

Actel rolled out SmartFusion intelligent mixed signal FPGA reference designs for motor control applications. The reference designs are implemented in a single A2F500 SmartFusion device controlling up to four axes of permanent magnet synchronous motors (PMSMs) simultaneously using the Field Oriented Control (FOC) algorithm. The reference design package includes an example of FOC implementation using space vector pulse width modulation (SVPWM) on the SmartFusion device while using various feedback methods such as optical encoders and Hall effect sensors. The reference design package (A2F-MOTOR-CONTROL-DESIGNS) is available for a list price of $499.

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LatticeXP2 Brevia Development Kit and Reference Designs

Lattice Semiconductor introduced the LatticeXP2 Brevia Development Kit and 28 new silicon-proven reference designs for developing high volume, cost sensitive, high density applications. The LatticeXP2 Brevia Development Kit features the LatticeXP2 LFXP2-5E-6TN144C device, 2Mb SPI Flash and 1Mb SRAM memory, expansion headers and several LEDs and user switches. Promotional pricing for the LatticeXP2 Brevia Development Kit is $29 for kits shipped through August 31, 2010. The regular list price of the Brevia Development Kit will be $49 after the initial promotional period.

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Lattice MachXO Control Development Kit

Lattice Semiconductor introduced the new MachXO Control Development Kit and 12 new reference designs for prototyping system control functions such as temperature and current monitoring, power supply sequencing, fan control and fault logging, that are commonly found in telecom infrastructure, server, industrial and medical applications. The MachXO kit enables the development of system control designs for designers of CPLDs and low-density FPGAs. Promotional pricing for the MachXO Control Development Kit is $119.

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