Analog Devices recently launched the JESD204B Xilinx Transceiver Debug Tool. The FPGA-based reference design with software and HDL code reduces the design risk of high-speed systems incorporating JESD204B-compatible converters. It supports the 312.5-Mbps to 12.5-Gbps JESD204B data converter-to-FPGA serial data interface and Xilinx Inc., 7 series FPGAs and Zynq-7000 All Programmable SoCs.
Xilinx introduced their Virtex-7 FPGA VC709 Connectivity Kit. The tool is a 40 Gbps platform that enables designers to accelerate design productivity for high-bandwidth and high-performance applications, such as network interface cards for security, network monitoring, and high frequency trading appliances. The Virtex-7 FPGA VC709 Connectivity Kit is available now for shipping. It is priced at $4,995.
Barco Silex released the multi-channel Video over IP with JPEG 2000 reference design. The VoIP reference design integrates the BarcoSilex JPEG 2000 Encoder and Decoder IP Cores, the Barco Silex high-performance memory controller core, and the Xilinx SMPTE 2022-1/2 and Ethernet MAC LogiCORE IP Cores for Xilinx 7 Series FPGAs and Zynq All Programmable SoC.
Altera introduced a direct memory access (DMA) reference design. The solution is constructed for Stratix V customers needing to seamlessly and quickly design PCIe Gen3 solutions. Stratix V GX FPGAs feature a hardened protocol stack for PCIe Gen3 applications, demanding the highest in bandwidth, system integration and flexibility, at a reduced cost with lower total power consumption. The new DMA reference design makes it fast and easy to develop high-performance PCIe Gen3x8 hardware.
Lattice Semiconductor recently introduced the SensorExtender reference design. The Sensor Extender is a low-cost solution for remotely locating image sensors up to eight meters away from the image signal processor (ISP) and transmit and receive video signals at resolutions that range up to 720p60 and 1080p30. The reference design is tested with the Aptina MT MT9M024 and the Lattice HDR-60 camera development kit’s base board.
Altera and Flexibilis developed a High-availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP) reference design. It features Flexibilis Redundant Switch (FRS) intellectual property (IP) implemented on an Altera low-power, low-cost Cyclone-class FPGA or Cyclone V SoC. The reference design simplifies development and implementation of highly reliable mission-critical communications systems in smart grid substation automation equipment.
Lattice Semiconductor introduced a serial sub-LVDS bridge reference design for the Sony IMX136 and IMX104 image sensors. Lattice’s image sensor bridge design helps engineers quickly introduce cameras based on the Sony IMX136 and IMX104. The image sensor bridge design is available now for download, and the MachXO2-1200 (featured in the reference design) is in full production.
Maxim Integrated Products introduced a reference design that will protect Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The reference design features security software (from Maxim or Xilinx) and the Maxim DS28E01-100 1-Wire secure memory device. Engineers can easily add a level of design security to products with the Maxim DS28E01-100 1-Wire secure memory device. In the future, the reference design will support Artix-7, Kintex-7, Virtex-7 and the Zynq-7000 FPGA devices.
Microsemi recently introduced a LCD display reference design for industrial and medical applications. The reference design is based on the SmartFusion customizable system-on-chip. The SmartFusion cSoC integrates FPGA technology with a hardened ARM Cortex-M3 processor and programmable analog blocks. The SmartFusion display reference design source files and user’s guide are available now.
Lattice Semiconductor and Aptina will showcase a low cost, dual image sensor design at the Consumer Electronics Show (CES) in Las Vegas, January 10-13, 2012. The dual image sensor design helps ISP vendors to quickly offer multiple camera solutions for the consumer market. Lattice’s private hospitality meeting suite will be held in the Las Vegas Hilton, North Hall, 28th Floor, Suite 127.