Lattice Semiconductor introduced the Platform Manager mixed-signal devices family. Platform Manager devices integrate programmable analog and logic to support many common functions, such as power management, digital housekeeping and glue logic. Platform Manager devices are available in commercial and industrial temperature ranges, and are available in environmentally friendly Lead-Free/Halogen-Free packages. High volume pricing for the LPTM10-1247 device in a 128-pin TQFP package is $3.75. Samples are available now.
Lattice Semiconductor introduced the SPI4 Intellectual Property (IP) core for OIF-compliant System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1). The full rate solution is based on LatticeECP3 Field Programmable Gate Arrays (FPGAs). The SPI-4.2 soft IP core supports up to 256 data channels with aggregate throughputs of between 3 and 12.8Gbps and can be used to connect network processors with OC192 framers, mappers, and fabrics, as well as Gigabit and 10-Gigabit Ethernet MACs. The Lattice SPI-4.2 IP core is available now ($3,000 list price).
Actel launched SmartFusion, which is industry first intelligent mixed signal FPGA. SmartFusion devices feature Actel’s ProASIC 3 FPGA architecture, a complete microcontroller subsystem built around a hard ARM Cortex-M3 processor, and programmable analog blocks on a flash process. SmartFusion devices are ideal for motor control, system and power management and industrial automation. SmartFusion A2F200 devices are now available in volume production. A2F500 devices are scheduled for delivery in Q2 2010 and A2F060 devices are expected at the second half of the year.
SiliconBlue Technologies introduced the iCE65L01 mobileFPGA device. The iCE65L01 mobileFPGA device offers the benefits of programmability and time-to-market to handheld, mobile product designers. The ASIC-like cost, high logic capacity, ultra-low power, and advanced-package technology of the iCE65 devices provides the scalability required for designers to implement features that differentiate their products. The iCE65L01 features 1,280 logic cells and up to 93 user I/O pins.
Pentek announced the 7753 and 7853 beamformer PCIe modules. Each model is a high-speed software radio board for processing baseband RF or IF signals and incorporates unique and powerful beamforming functions. Created to accelerate system level design and lower system cost, the boards bring high-performance built-in features and connectivity to PC platforms. Software support packages are available for Linux, Windows, and VxWorks operating systems. Larger FPGAs are available enabling customers to do their own programming with GateFlow. Starting price for the 7753 and the 7853 starts at $15,795 and $14,195 ($USD), respectively. Delivery is 8 to 10 weeks ARO.
Lattice Semiconductor introduced an evaluation board for the ispClock 5400D programmable clock device. The evaluation board is an easy-to-use platform for evaluating and designing with the ispClock5400D differential clock distribution device. The evaluation board can be used by itself to review the performance and in-system programmability of the 5400D device, or as a companion board and clock source for LatticeECP3 FPGA Serial Protocol or Video Protocol evaluation boards. The ispClock5400D evaluation board is priced at $169.
Impulse Accelerated Technologies developed a FPGA-based financial feed and network packet parsing solution to Athena Capital Research LLC, a quantitative investment manager based in New York City. Impulse offers customer-programmable feed handling solutions for use in automated trading, arbitrage and real-time analytics. FPGAs are increasingly finding their way into financial feed management operations due to their inherently deterministic behavior and ability to support ultra-low latency and reduced power consumption relative to software-based solutions.
Lattice Semiconductor has licensed the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family from Praesum. Lattice has full rights to use and sub-license the Serial RapidIO IP core. The core supports 1x, 2x, and 4x lane configurations at up to 3.125Gbps lane speeds, offering the lowest cost, lowest power programmable SRIO solution in the industry. The Serial RapidIO 2.1 IP core is available for immediate evaluation and use.
QuickLogic is shipping engineering samples of its low power ArcticLink II VX2 solution platform. ArcticLink II VX2 is ideal for display path CSSPs for smartphones, multimedia phones, feature phones, mobile internet devices (MIDs), netbooks, smartbooks, mobile TV devices, and portable navigation devices (PNDs). CSSPs based on the ArcticLink II VX2 solution platform are sampling now, and are scheduled for full production availability in Q4, 2009.
Xilinx and ARM will enable ARM processor and interconnect technology on Xilinx FPGAs. Xilinx is adopting ARM Cortex processor IP, using performance-optimized ARM cell libraries and embedded memories for their future programmable platforms. In addition, ARM and Xilinx are working to define the next-generation ARM AMBA interconnect technology that is enhanced and optimized for FPGA architectures. Ideal applications will span the communications, automotive, consumer, aerospace, defense, and industrial markets.