Lattice Semiconductor announced the iCE40 LP384 FPGA. It is the smallest member of the iCE40 family of ultra-low density FPGAs. The iCE40 LP384 FPGA architecture is ideal for capturing and processing large amounts of data at hardware speeds while using very little power and board space. The iCE40 LP384 FPGA devices are available in sample quantities. Present packaging options include 32-pin QFNs (5.0 mm x 5.0 mm), 36-ball ucBGAs (2.5 mm x 2.5 mm), and 49-pin ucBGAs (3.0 mm x 3.0 mm).
Lattice Semiconductor will host a series of seminars on their MachXO2 and LatticeECP3 devices. The 2011 Programmable Logic Seminars feature advanced programmable logic concepts, basic design principles and real-world application examples. The seminars will also demonstrate MachXO2- and LatticeECP3-based evaluation kits. Attendees will receive a copy of the seminar materials and Lattice Diamond design software. The free events will take place in over 50 cities in Asia, Europe and North America.
Lauterbach’s TRACE32 development tool now supports the Xilinx Zynq-7000 Extensible Processing Platform, which includes a complete ARM Cortex-A9 MPCore processor-based system with 28nm low-power programmable logic.
Xilinx introduced the Zynq-7000 Extensible Processing Platform (EPP). The family consists of the Zynq-7010, Zynq-7020, Zynq-7030 and Zynq-7040 devices. The Zynq-7000 family combines an ARM Cortex-A9 MPCore processor-based system with 28nm, low-power programmable logic. The first silicon devices will be available in the second half of 2011. Engineering samples are expected in the first half of 2012. The Zynq-7000 family will have an entry point of below $15 in high volumes. The Zynq-7000 EPP family is ideal for video surveillance, automotive driver assistance, factory automation, and other embedded applications.
Altera became the first company to demonstrate 25-Gbps transceiver performance in programmable logic. Altera achieved this with their 28nm transceiver test chip, which is a prototyping platform that Altera is using to deploy 28-Gbps transceivers on 28nm FPGAs. The 25-Gbps more than doubles the transceiver performance in currently available FPGA solutions.
Tokyo Electron Device has developed an IP core compatible with the MECHATROLINK-III standard for implementation with the low-cost Xilinx Spartan-6 FPGA family. The MECHATROLINK-III specification is an open motion field network communications standard established by the Iruma, Saitama Prefecture, Japan-based MECHATROLINK Members Association. Tokyo Electron Device’s MECHATROLINK-III compliant IP core for Spartan-6 FPGAs will be available in the third quarter of this year.
The EE Times Virtual Conference titled, Maximizing the Flexibility of FPGAs, will take place Thursday, June 24th from 11:00am to 6:00pm EDT. The virtual conference features speeches, webinars, discussion panels, and live interactive chats on the topic of programmable logic and the design flexibility it allows. The online event will take place on your computer.
SiliconBlue will distribute a version of the Synopsys Synplify Pro FPGA synthesis software with their iCEcube software. The included version of the Synplify ProFPGA synthesis software is optimized for iCE65 family of mobileFPGA devices.