Tag Archives: PLDA

PLDA QuickUDP 10Gb UDP Hardware Stack IP Core for Altera and Xilinx FPGAs

PLDA QuickUDP 10Gb UDP Hardware stack IP core for FPGA devices

PLDA introduced their QuickUDP, which is a 10Gb UDP Hardware stack IP core for FPGA devices. The QuickUDP IP solution is a 100% RTL-designed IP, compliant with the IEEE802.3 specification and supports the ARP, IPv4, ICMP, IGMP, and UDP protocols. The PLDA QuickUDP 10G UDP Hardware Stack IP is available now from PLDA. The PLDA QuickUDP can be integrated into Altera-based and Xilinx-based FPGA designs.

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PLDA XpressV7-LP PCIe FPGA Design Kit Features Xilinx Virtex-7 FPGA

The XpressV7-LP is PLDA’s latest FPGA design kit. The XpressV7-LP features a FPGA-based low-profile PCI Express form factor card with 40Gb of Ethernet connectivity and 8 GBytes of DDR3 SDRAM. The FPGA kit is delivered with PLDA’s PCIe 3.0 IP and optional 10G UDP/TCP stack IP, specifically optimized for the Xilinx Virtex-7 FPGA. The PLDA XpressV7-LP FPGA Design Kit will ship in October.

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PLDA Introduces XpressGX5LP FPGA Design Kit

PLDA XpressGX5LP FPGA design kit

PLDA introduced their XpressGX5LP FPGA design kit. It is the first FPGA-based low-profile PCI Express form factor card featuring 40Gb of Ethernet connectivity and 8 GBytes of DDR3 SDRAM. It is delivered with PLDA’s PCIe 3.0 IP and full hardware 10G TCP stack IP, specifically optimized for the Altera Stratix V FPGA. The PLDA XpressGX5LP is shipping now and will available for volume orders in Q3 2012.

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PLDA Unveils QuickTCP 10G TCP/IP Stack IP Core for Altera, Xilinx FPGA

PLDA recently introduced their QuickTCP IP, which is a 10Gb TCP/IP Hardware stack IP core. It features an AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs. PLDA QuickTCP is a 100% RTL designed IP. It is compliant with the IEEE802.3 specification and supporting the ARP, IPv4, ICMP, and TCP protocols. The PLDA QuickTCP IP solution is available now from PLDA.

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PLDA EZDMA IP Solution

The PLDA’s EZDMA IP is a DMA solution. The IP features a vendor-agnostic user interface and seamless device migration. It is configurable for resource optimization and customizable to fit specific customer requirements. The PLDA EZDMA solution supports the Aldec Riviera-PRO for Linux and Active-HDL for Windows verification tools for FPGA development. PLDA’s EZDMA IP solution is available now for PCI Express Gen1 and Gen2 designs.

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PLDA XpressRich3 PCI Express 3.0 Based IP Core for FPGA, ASIC Devices

PLDA introduced the XpressRich3 IP core for FPGAs and ASICs based on the forthcoming PCIe 3.0 specification, currently under development within the PCI-SIG. The PLDA XpressRich3 core features an architecture that seamlessly allows both ASIC and FPGA implementations. The PLDA XpressRich3 IP will be available for review at the PCI-SIG Developers Conference, which will be held on June 23-24, 2010 in Santa Clara, California.

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