Xilinx recently introduced the Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE, CPRI v4.1 LogiCORE, and JESD204B v.1.1 LogiCORE IP cores. The Xilinx three LogiCORE IP cores support connectivity standards and will help developers address design challenges in building new wireless equipment with higher system capacities. The Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP, JESD204 v1.1 LogiCORE IP , and CPRI v4.1 LogiCORE IP are ideal for building programmable, flexible and cost effective 3G+/4G wireless base stations. They are available in Xilinx’s ISE Design Suite 13.3 and can be evaluated free of charge.
CoWare announced the 2010.1 release of CoWare SPW products. The SPW 2010.1 release advances the LTE (Long Term Evolution) Wireless Reference Library and adds a complete Xilinx implementation flow that includes direct source translation technology from C Data Flow (CDF) into RTL. The CoWare SPW 2010.1 release is available immediately. With this release, CoWare has reverted back to the product’s original SPW name (previously Signal Processing Designer, SPD).
CoWare has integrated and is distributing models of Xilinx’s LTE Baseband IP portfolio with their SPW LTE solution. By combining the SPW LTE solution with Xilinx’s Virtex and Spartan FPGA devices, engineers implementing advanced 4G basestations will be able to reduce system integration and optimization time. The CoWare SPW Library for Xilinx LTE IP is available for shipment now.