Lattice Semiconductor had upgraded their HDR-60 Video Camera Development Kit. The Lattice HDR-60 is now enhanced with a Helion Graphical User Interface (GUI). The new GUI makes the engineer’s job even easier. It offers ease-of-use while improving design accuracy, further enhancing the user experience. The enhanced HDR-60 GUI will be available for download next week at no additional charge to current and new customers of the Lattice HDR-60 Video Camera Development Kit.
Lattice Semiconductor Corporation is offering low power, high speed, and small form-factor versions of their LatticeECP3 FPGA devices. The new packaging helps engineers create power and space limited applications in professional cameras, surveillance cameras, medical imaging, video communication, and small-form-factor wireline and wireless appliances. Prices for the LatticeECP3-17K Mini Device in 328csBGA package start at $4.95 (in 500K unit volume). Delivery will be in the fourth quarter of 2013.
According to Lattice Semiconductor, their solution is interoperable with existing PCIe 2.0 supported systems. At a recent PCI-SIG workshop, the LatticeECP3 FPGA and its PCI Express (PCIe) IP core passed PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations. As a result, the LatticeECP3 FPGA family is now compliant with the PCI Express 2.0 specification at 2.5Gbps. Lattice also worked with Trellisys on a PCIe Bus Functional Model (BFM) for Lattice’s PCI Express x1 and x4 IP Cores.
Lattice Semiconductor and Flexibilis introduced Flexibilis Ethernet Switch (FES) IP cores for LatticeECP3 FPGAs. The Ethernet switch IP cores can operate at 10Mbps/100Mbps/1Gbps, support Ethernet Layer 2, switch with Gigabit forwarding capacity per port, support Quality of Service with up to four queues per port, and support Gigabit Fiber optic and Gigabit twisted pair copper Ethernet interfaces. The FES IP cores are ideal for smart grid substation automation, networked industrial automation gear, and high availability network equipment.
Lattice Semiconductor and Oregano Systems introduced IEEE-1588 Timing Node System IP cores for the LatticeECP3 and LatticeECP2M FPGA families. The SoC-class IP cores are syn1588 Clock_S, syn1588 Clock_M, and syn1588 VIP. The syn1588 VIP is a single chip IEEE 1588 solution. The syn1588 Clock_S IP core offers the full syn1588 technology with a minimum amount of resources required. The syn1588 Clock_M IP core offers the full syn1588 technology with support for trigger and IO events. The Oregano clock cores are compatible to the IEEE1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems.
Lattice Semiconductor has extended the Serial RapidIO 2.1, Level 1 endpoint core to support 4 x 3.125Gbps. The previous version of the LatticeECP3 FPGA IP core supported 1x and 2x up to 3.125Gbps and 4x up to 2.5Gbps. The Lattice core can be used with the Lattice Advanced Mezzanine Card (AMC) form factor platform. The Serial RapidIO 2.1 IP core and associated AMC platform are available now for evaluation and use.
Lattice Semiconductor will host a series of seminars on their MachXO2 and LatticeECP3 devices. The 2011 Programmable Logic Seminars feature advanced programmable logic concepts, basic design principles and real-world application examples. The seminars will also demonstrate MachXO2- and LatticeECP3-based evaluation kits. Attendees will receive a copy of the seminar materials and Lattice Diamond design software. The free events will take place in over 50 cities in Asia, Europe and North America.
Lattice Semiconductor and Helion Technology teamed on a family of compression and encryption IP cores for the LatticeECP3 FPGA devices. The new portfolio consists of the Payload Compression System core, LZRW lossless compression core, Fast Hash core, and Modular Exponentiation core. The compression and encryption IP cores for the LatticeECP3 FPGA are available now.
Lattice Semiconductor launched their HDR-60 Video Camera Development Kit, which is a production-ready High Definition (HD) video camera development system based on the LatticeECP3 FPGA family. The HDR-60 kit helps camera manufacturers jump start their FPGA-based high definition camera programs. The kit features Aptina 720p HDR sensor, on-board DDR2 memory, two USB ports, RJ45 Ethernet port, Broadcom Broadreach PHY, and built-in BNC connector. The Lattice HDR-60 Video Camera Development Kit is available for $399.
Lattice Semiconductor introduced five new Intellectual Property (IP) suites: PCI Express, Ethernet Networking, Digital Signal Processing, Video & Display, and Value. The IP suites are economical packages of IP cores that allow designers easily obtain critical functions for their applications. Lattice IP Suites will help accelerate the design of electronic systems with the LatticeECP3 FPGA devices. The suites offer ready-made building blocks for solving problems like high-speed data transfer, Ethernet networking, high speed memory interfaces, digital signal processing and video pixel processing.