Altera now offers a fully verified EtherCAT (Ethernet for Control Automation Technology) protocol intellectual property (IP) for Altera FPGAs. With the offering, engineers can leverage the performance and integrate a discrete EtherCAT device in an existing FPGA with confidence and minimum effort.
Altera and Flexibilis developed a High-availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP) reference design. It features Flexibilis Redundant Switch (FRS) intellectual property (IP) implemented on an Altera low-power, low-cost Cyclone-class FPGA or Cyclone V SoC. The reference design simplifies development and implementation of highly reliable mission-critical communications systems in smart grid substation automation equipment.
PLDA introduced their QuickUDP, which is a 10Gb UDP Hardware stack IP core for FPGA devices. The QuickUDP IP solution is a 100% RTL-designed IP, compliant with the IEEE802.3 specification and supports the ARP, IPv4, ICMP, IGMP, and UDP protocols. The PLDA QuickUDP 10G UDP Hardware Stack IP is available now from PLDA. The PLDA QuickUDP can be integrated into Altera-based and Xilinx-based FPGA designs.
Altera introduced a single-chip, multi-rate OTN (optical transport network) muxponder solution for 100G network aggregation. The multi-rate muxponder IP solution is based on Altera’s 28nm Stratix V FPGA devices. The solution enables engineers to customize systems and target FPGA architectures that are optimized for specific design requirements. The multirate 100G muxponder IP solution expands the capabilities of current networks by enabling developers to integrate emerging client types into their networks, such as 16G Fibre Channel.
Altera revealed plans for their next generation of 20nm products. According to the company, they will offer a system-integration platform that combines the hardware programmability of FPGAs with the software flexibility of digital signal processors and microprocessors along with the efficiencies of application-specific hard intellectual property (IP). Altera’s next-generation devices leverage TSMC’s 20nm process technology. 20nm system-on-chip (SoC) FPGAs provide engineers a software migration path from 28nm to 20nm while delivering a 50% processor subsystem performance increase.
Xilinx announced Vivado Design Suite 2012.2. This is the first public release of their next-generation design environment. The Xilinx Vivado Design Suite is an IP and system-centric design environment built from the ground up to accelerate the design of not only programmable logic and I/O but all programmable devices. The Vivado Design Suite 2012.2 is now available at no additional cost to all ISE Design Suite customers who are currently in warranty.
Lattice Semiconductor and Leopard Imaging introduced a dual camera module kit. The dual HD IP camera solution enables the TI DaVinci TMS320DM368 video processor to interface to two 720p image sensors. This kit is ideal for engineers designing black box car drive recorders or other applications that require two cameras. For black box car drive recorder applications, one camera can be pointed out the front of the vehicle, while the other can be directed toward the driver. The dual camera module kit is available now for $399 from Leopard Imaging.
Altera announced the production availability of their 40-Gbps Ethernet and 100-Gbps Ethernet intellectual property cores. The cores can be used to create high-performance, low-cost, subsystem IP in Stratix IV and Stratix V FPGAs. Altera’s 40GbE and 100GbE IP cores are compatible with the recently announced Quartus II software v12.0. They are available for download on the Altera website.
Altera and TSMC teamed on a heterogeneous 3D IC test vehicle. The process uses TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process. Altera is the first semiconductor company to develop and complete characterization of a heterogeneous test vehicle using TSMC’s CoWoS process. This and additional test vehicles enable Altera to quickly test the capabilities and reliability of 3D ICs to ensure they meet yield and performance targets.
Altera and Eutecus teamed together on a FPGA-based video analytics solution. It is based on the Cyclone IV FPGA and features the Eutecus’ Multi-Core Video Analytics Engine (MVE) intellectual property (IP). The MVE performs the analytics functions in the FPGA. Their solution is the first FPGA-based full-HD 1080p/(30 frames per second) 30fps video analytics on a Cyclone IV FPGA. The IP and FPGA can be purchased directly from Altera, which simplifies the development of a video surveillance system.