Tag Archives: IP Cores

Barco Silex Debuts Multi-channel Video over IP with JPEG 2000 Reference Design

Barco Silex multi-channel Video over IP with JPEG 2000 reference design

Barco Silex released the multi-channel Video over IP with JPEG 2000 reference design. The VoIP reference design integrates the BarcoSilex JPEG 2000 Encoder and Decoder IP Cores, the Barco Silex high-performance memory controller core, and the Xilinx SMPTE 2022-1/2 and Ethernet MAC LogiCORE IP Cores for Xilinx 7 Series FPGAs and Zynq All Programmable SoC.

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CAST Offers Ultra-low Latency Video Encoding Option for H.264 IP Cores

CAST announced an ultra-low latency video encoding option for their H.264 video encoder IP cores. The new option enables near-real time video transmission for streaming and wireless video applications, especially when coupled with CAST’s hardware stacks for fast, processor-less video processing.

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Microsemi EnforcIT Cryptography IP Cores Achieves NIST Certification

Microsemi has achieved National Institute of Standards and Technology (NIST) algorithmic certification on their U.S.-developed EnforcIT Cryptography Suite of National Security Agency (NSA) Suite B algorithms. The EnforcIT Cryptography Suite was validated by InfoGard Laboratories, Inc. and certified by the NIST. The certification is expected to be posted to the NIST website later this month.

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RFEL Announces New FPGA Video Processing IP Cores

RFEL announced a new family of video processing IP cores. The IP FPGA cores can be supplied with standard software interface frameworks to simplify their deployment. If required, RFEL can modify the cores to meet the requirements of constrained resources or legacy platforms. The new video processing FPGA IP cores are available now, either as standalone cores or as part of a system solution created by RFEL to meet a customer’s requirements.

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Xilinx Introduces Dual 100 Gbps Gearbox Solution

Xilinx introduced their dual 100G Gearbox solution, which features a 28nm Virtex-7 HT FPGA and dual 100G Gearbox intellectual property cores. The new Xilinx solution enables equipment vendors to connect 100 Gbps interfaces with up to two CFP2 optical modules while lowering the overall BOM by reducing chip count and allowing integration with OTN framers as well as 100G bridges into a single chip. The programmability of the Virtex-7 HT FPGA ensures that the equipment vendors can easily keep up with changes in standards that are still evolving in the optical, Ethernet and OTN market space.

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Serial RapidIO Gen 2 v1.2 Endpoint, CPRI v4.1, and JESD204B v.1.1 IP Cores

Xilinx recently introduced the Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE, CPRI v4.1 LogiCORE, and JESD204B v.1.1 LogiCORE IP cores. The Xilinx three LogiCORE IP cores support connectivity standards and will help developers address design challenges in building new wireless equipment with higher system capacities. The Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP, JESD204 v1.1 LogiCORE IP , and CPRI v4.1 LogiCORE IP are ideal for building programmable, flexible and cost effective 3G+/4G wireless base stations. They are available in Xilinx’s ISE Design Suite 13.3 and can be evaluated free of charge.

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RF Engines HyperSpeed Plus Pipeline Fast Fourier Transform IP Cores

RF Engines has enhanced its HyperSpeed PFFT cores from its family of Digital Signal Processing (DSP) solutions to create the new HyperSpeed Plus cores. The Pipeline Fast Fourier Transform (PFFT) IP cores feature data rates in excess of 52 Giga samples per second (2048 point FFT implemented on a Xilinx Virtex-6 FPGA device). The HyperSpeed Plus cores are available now for licence in netlist form from RFEL.

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CAST 32-bit BA22 Processor Cores for Embedded Systems

CAST announced their royalty-free BA22 Processor IP Family for ASICs and FPGAs. The new IP cores are based on the BA22 design sourced from Beyond Semiconductor. The BA22 processor cores feature pipelined 32-bit RISC BA22 architecture, caches and memory management units, up to 32 general purpose registers, enhanced arithmetic processing capabilities (divider and floating point units), power-management unit, interactive JTAG-based debug capability, 1.41 DMIPS/MHz, frequencies from 50 MHz to over 300 MHz, 12,000 to 38,000 gates, and require only 0.023 mW/MHz (in a 65nm process).

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Flexibilis Ethernet Switch IP Cores for LatticeECP3 FPGA Devices

Lattice Semiconductor and Flexibilis introduced Flexibilis Ethernet Switch (FES) IP cores for LatticeECP3 FPGAs. The Ethernet switch IP cores can operate at 10Mbps/100Mbps/1Gbps, support Ethernet Layer 2, switch with Gigabit forwarding capacity per port, support Quality of Service with up to four queues per port, and support Gigabit Fiber optic and Gigabit twisted pair copper Ethernet interfaces. The FES IP cores are ideal for smart grid substation automation, networked industrial automation gear, and high availability network equipment.

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Xilinx Goes Shopping Again, Acquires Sarance Technologies

Xilinx has acquired Sarance Technologies. The acquisition will help Xilinx increase and accelerate the displacement of ASSPs and ASICs in many 40G/100G and beyond programs. Sarance Technologies is a supplier of ASIC and FPGA IP cores for packet processing. The cores include Interlaken IP, classification and traffic management IP.

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