Altera now offers a fully verified EtherCAT (Ethernet for Control Automation Technology) protocol intellectual property (IP) for Altera FPGAs. With the offering, engineers can leverage the performance and integrate a discrete EtherCAT device in an existing FPGA with confidence and minimum effort.
Altera revealed plans for their next generation of 20nm products. According to the company, they will offer a system-integration platform that combines the hardware programmability of FPGAs with the software flexibility of digital signal processors and microprocessors along with the efficiencies of application-specific hard intellectual property (IP). Altera’s next-generation devices leverage TSMC’s 20nm process technology. 20nm system-on-chip (SoC) FPGAs provide engineers a software migration path from 28nm to 20nm while delivering a 50% processor subsystem performance increase.
Altera announced the production availability of their 40-Gbps Ethernet and 100-Gbps Ethernet intellectual property cores. The cores can be used to create high-performance, low-cost, subsystem IP in Stratix IV and Stratix V FPGAs. Altera’s 40GbE and 100GbE IP cores are compatible with the recently announced Quartus II software v12.0. They are available for download on the Altera website.
Altera and Eutecus teamed together on a FPGA-based video analytics solution. It is based on the Cyclone IV FPGA and features the Eutecus’ Multi-Core Video Analytics Engine (MVE) intellectual property (IP). The MVE performs the analytics functions in the FPGA. Their solution is the first FPGA-based full-HD 1080p/(30 frames per second) 30fps video analytics on a Cyclone IV FPGA. The IP and FPGA can be purchased directly from Altera, which simplifies the development of a video surveillance system.
Barco Silex announced the BA414E Public Key Crypto Engine Intellectual Property (IP) core. The BA414E is based on a scalable, highly pipelined and optimized arithmetic unit. The BA414E PK Crypto Engine can be mapped to any existing FPGA technology and all ASIC processes with reconfigurable elementary DSP blocks. The BA414E IP does not require any assistance from the main CPU to handle the complete Public Key processing. Based on a cost-effective µ-coded sequencer (coupled to a µ-DMA), the core can support complex operations and algorithms like RSA, CRT, DSA and ECDSA (including pre- and post-processing).
Lattice Semiconductor introduced five new Intellectual Property (IP) suites: PCI Express, Ethernet Networking, Digital Signal Processing, Video & Display, and Value. The IP suites are economical packages of IP cores that allow designers easily obtain critical functions for their applications. Lattice IP Suites will help accelerate the design of electronic systems with the LatticeECP3 FPGA devices. The suites offer ready-made building blocks for solving problems like high-speed data transfer, Ethernet networking, high speed memory interfaces, digital signal processing and video pixel processing.
Lattice Semiconductor introduced the SPI4 Intellectual Property (IP) core for OIF-compliant System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1). The full rate solution is based on LatticeECP3 Field Programmable Gate Arrays (FPGAs). The SPI-4.2 soft IP core supports up to 256 data channels with aggregate throughputs of between 3 and 12.8Gbps and can be used to connect network processors with OC192 framers, mappers, and fabrics, as well as Gigabit and 10-Gigabit Ethernet MACs. The Lattice SPI-4.2 IP core is available now ($3,000 list price).
Actel introduced intellectual property (IP) cores for SmartFusion intelligent mixed signal FPGAs. A large library of Actel IP cores are included in the Libero Integrated Design Environment (IDE) IP bundle, with obfuscated-RTL version included with the free Libero Gold license, and RTL-source version included with the $2,500 Libero Platinum license. The library of Actel’s IP cores can be configured and connected in the Libero IDE SmartDesign IP design tool.
Altera introduced their Serial RapidIO intellectual property (IP) core for the RapidIO 2.1 specification. Altera’s Serial RapidIO IP core supports up to four lanes at 5.0 GBaud per lane, addressing the increased bandwidth and reliability needs of the wireless and military markets. The IP core is optimized for Stratix IV FPGAs with embedded transceivers and is supported within Quartus II software v9.1.