Tag Archives: HDL

MathWorks Launches HDL Coder and HDL Verifier HDL Code Generation Tools

MathWorks introduced HDL Coder and HDL Verifier. HDL Coder automatically generates HDL code from MATLAB and helps engineers implement FPGA and ASIC designs from the MATLAB language. HDL Verifier features FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs. HDL Coder and HDL Verifier are available now. Pricing for HDL Verifier starts at $3,250 and pricing for HDL Coder starts at $10,000. With HDL Verifier and HDL Coder, MathWorks now provides HDL code generation and verification across their MATLAB and Simulink tools.

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ADI AD9739A D/A, AD9467 A/D Boards Support Xilinx FPGA Targeted Design Platforms

Analog Devices unveiled the AD9739A D/A converter and AD9467 A/D converter FMC boards. The two data converter FPGA mezzanine cards can connect to Xilinx’s new 28nm 7 series field programmable gate array evaluation kits. The Analog Devices FMC boards support multiple generations of Xilinx kits (including the new Kintex-7 FPGA evaluation kits). The ADI FMC boards include all of the HDL (hardware description language) code and device drivers needed for designers to engage in rapid prototyping and reduce development time and risk.

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MathWorks EDA Simulator Link v3.3

MathWorks rolled out version 3.3 of their EDA Simulator Link. The latest version features FPGA-in-the-loop (FIL) capabilities for Xilinx FPGA development boards. FIL enables engineers to verify their designs at hardware speeds while using Simulink as a system-level test bench. EDA Simulator Link v3.3 is available now with prices starting at $2000 (US list price).

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Lattice ispLEVER Classic 1.4 Design Tool Suite

Lattice Semiconductor launched ispLEVER Classic design tool suite, version 1.4. The upgraded ispLEVER Classic features Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH 4000ZE CPLD fitter with improved power optimization. Classic 1.4 software is compatible with Windows XP/Vista/7 and operates as a 32-bit application. The ispLEVER Classic 1.4 tool suite is available now for free. Designers can also download the optional Synopsys Synplify Pro logic synthesis and Aldec Active-HDL simulator modules.

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SynaptiCAD Upgrades WaveFormer Lite

SynaptiCAD rolled out an upgraded version of WaveFormer Lite. WaveFormer Lite is an entry level tool that can generate VHDL and Verilog stimulus-based test benches for the Actel Libero design software and other FPGA/ASIC vendor flows without requiring any special runtime engines. WaveFormer Lite fits seamlessly into Actel’s design environment, automatically extracting signal information from your HDL design files, and producing HDL test bench code that can be used with any standard VHDL or Verilog simulator.

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RocketDrive FPGA Verification and Debug Solution Supports Virtex-6

The latest versions of GateRocket’s RocketDrive FPGA verification and debug solution will roll out in July 2010. RocketDrive reduces verification and debug time by integrating the FPGA into the HDL simulator to provide a “hardware in the loop” process based on GateRocket’s Device Native methodology. This technique combines the actual FPGA hardware and RTL simulation models in the same verification run and allows execution of the design on the target FPGA device. The new version features support for Xilinx Virtex-6 programmable devices. Pricing starts at $25,000.

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Lattice Semiconductor PAC-Designer 5.2

Version 5.2 of Lattice Semiconductor’s PAC-Designer mixed signal design tool suite features new device support and productivity features. PAC-Designer software is the tool suite for the design and verification tool of Lattice mixed signal devices. The PAC-Designer software is a complete design environment, including everything needed for design, implementation, simulation, and programming of supported devices. Lattice’s PAC-Designer software for Windows is available now at no charge for download.

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