CAST announced the H.264 Video Over IP – HD Encoder Subsystem. The reusable subsystem makes it easier to build video streaming into mobile and other products. Reference designs for the streaming subsystem are available now for the Altera Stratix IV and Arria V families, and the Xilinx Kintex-7 line. These include the CAST and other essential IP cores implemented in an FPGA, plus the necessary interfaces, memory, drivers, and software.
CAST announced an ultra-low latency video encoding option for their H.264 video encoder IP cores. The new option enables near-real time video transmission for streaming and wireless video applications, especially when coupled with CAST’s hardware stacks for fast, processor-less video processing.
CAST announced the H264-HP-E video encoder IP core. The ISO/IEC 14496-10 and ITU-T H.264 High Profile specification compliant H264-HP-E video encoder IP core is sourced from Alma Technologies. It is available now and is ideal for HD broadcast, professional video cameras, and video storage. An intra-only version features extremely low latency for real-time applications, and is suitable for AVC-Intra 50 and 100 implementations.
Vanguard Software Solutions introduced their AVC-I encoder and decoder core for FPGA devices. A SVC codec core will be available in the fourth quarter. In addition, VSS is also developing a new HEVC FPGA core that will be available next year. The HEVC core will provide customers with access to real-time, HEVC functionality with FPGA flexibility.
NTT Electronics has developed a FPGA version of a multi-standard single chip LSI for both H.264/AVC 4:2:2 10-bit (including AVC-Intra 100/50) and MPEG-2 4:2:2 decoding. The 1080p 60 FPGA version will be released in the first quarter of 2011. By 2012, NTT Electronics expects to have over 10 models of next-generation H.264/AVC encoder/decoder LSIs.
Silicon Image introduced the cineramIC 4K and 3D H.264 digital video decoder IP core. With its high performance, low cost and high-quality video imaging, the cineramIC IP core can be integrated into System-on-Chips (SoCs) for next-generation digital TV (DTV), set-top-box (STB) and camcorder applications, as well as professional video editing, broadcast, medical, and surveillance FPGA applications.
Jointwave introduced their H.264 series encoder IP core. The Jointwave IP cores support Level 1.0 to 5.1 of H.264 (MPEG-4 Part 10, also called AVC). The cores cover baseline profile, main profile, and high 4:2:2/4:4:4 profile. Compare to competitors’ solutions, Jointwave’s IP core uses less hardware resources. The H.264 encoder features ultra-low frequency, super low latency, small die size, and ultra-low power consumption. Jointwave H.264 IP core can be used without embedded or external CPU, and reduce the system complexity. It runs on FPGA and ASIC.