Reflex CES (Custom Embedded Systems) introduced the Aurora-like IP core. It is based on Altera FPGA devices. The Reflex CES IP core enables interoperability between Xilinx Virtex-6 LXT and Altera Stratix IV and Stratix V GX FPGAs. The Reflex CES Aurora-like 8B/10B IP Core is available now with VHDL source code, test-benches, a reference design and user guide. Reflex CES plans to ship an Aurora-like IP Core that supports communication between FPGAs with a 64B/66B protocol at 10 Gbps.
Altera released a software development kit for Open Computing Language. The tool is the FPGA industry’s first SDK for OpenCL. It combines the massively parallel architecture of a FPGA with the OpenCL parallel programming model. The Altera SDK for OpenCL is production ready and is available through the company’s early access program.
Xilinx introduced their fourth generation secure architecture with Information Assurance and Anti-Tamper IP core support for defense-grade 7 series FPGA devices and Zynq-7000 All Programmable system-on-chips. In addition to the secure capabilities, the defense-grade 7 series FPGAs and Zynq-7000 All Programmable SoCs offer mask set control, ruggedized packaging with fully-leaded (Pb) content for harsh environmental operation, full extended temperature range testing, long term availability and anti-counterfeiting features.
Xilinx has begun shipping their Artix-7 Field Programmable Gate Array (FPGA) family. The first device to ship is the Artix-7 A100T FPGA. Production qualification is scheduled for the first quarter of CY2013. The devices are ideal for edge applications. Designers can start developing Artix-7 family designs now with Xilinx design tools.
Microsemi’s RTAX-S/SL field programmable gate arrays have received QML Class V qualification. The U.S. Defense Logistics Agency (DLA) qualified the FPGA as Qualified Manufacturers List Class V in accordance with military performance standard MIL-PRF-38535 space-level qualification requirements. QML Class V is the highest standard in the industry for space integrated circuits. Microsemi radiation-tolerant RTAX-S/SL FPGAs are ideal for space-flight systems. They feature high performance, low power, single-chip form factor and live-at-power-up operation.
Microsemi’s radiation tolerant RT ProASIC 3 family of field programmable gate arrays (FPGAs) is now available in a ceramic quad flat pack (CQFP) package. Starting in April 2012, the Microsemi RT ProASIC3 FPGA devices will be available for prototyping in the CQ256 package. Fight units will be available by June 2012.
At DesignCon 2012, Xilinx will discuss the benefits and drawbacks of 3D IC standards. Xilinx will also present papers on Stacked Silicon interposer technology and the design benefits of using the Zynq-7000 Extensible Processing Platform (EPP). In addition, Xilinx will also demonstrate the latest Xilinx FPGA platforms featuring advanced Digital Signal Processing (DSP) performance, low power, FMC migration, high-speed connectivity, and Xilinx’s Agile Mixed Signal (AMS) Analog-to-Digital Converter (ADC). DesignCon 2012 will take place January 30 – February 2, 2012 in Santa Clara, California.
Xilinx rolled out version 13.4 of their ISE Design Suite. ISE Design Suite 13.4 features public access to the MicroBlaze Micro Controller System (MCS), new RX Margin Analysis and debug capabilities for the 28nm 7 Series FPGAs and partial reconfiguration support for the Artix-7 family and Virtex-7 XT devices. ISE Design Suite v13.4 is available now for all ISE Editions. List prices start at $2,995 for the Logic Edition.
In the latest Ben Heck Show episode, the modding guru discusses the benefits of using Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) to enhance LED-illumination projects. In the episode, Ben deconstructs the complex language of programmable logic devices as a means to help designers expedite their current builds as efficiently as possible.
Xilinx recently published a white paper about floating-point DSP algorithms. According to the technical paper, Xilinx System Generator for DSP enables the creation of custom precision datapaths for optimal area and power. The floating-point design flow generates an implementation that is bit- and cycle-accurate to the original simulation model. The title of the white paper is: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs. It was written by Tim Vanevenhoven.