Innovative Integration announced the ePC-K7 user-customizable, turnkey embedded instrument. The ePC-K7 embedded computer is a full Windows/Linux PC. It supports programmable Kintex 7 325/410 and Spartan 6 FPGAs and a wide variety of FMC modules. The ePC-K7 features a modular IO, scalable performance, and easy to use PC architecture. The embedded system reduces time-to-market.
Barco Silex released the multi-channel Video over IP with JPEG 2000 reference design. The VoIP reference design integrates the BarcoSilex JPEG 2000 Encoder and Decoder IP Cores, the Barco Silex high-performance memory controller core, and the Xilinx SMPTE 2022-1/2 and Ethernet MAC LogiCORE IP Cores for Xilinx 7 Series FPGAs and Zynq All Programmable SoC.
Altera and Micron Technology have successfully demonstrated interoperability between Altera Stratix V FPGAs and Micron’s Hybrid Memory Cube (HMC). This technology achievement enables system designers to evaluate today the benefits of HMC with FPGAs and SoCs for next-generation communications and high-performance computing designs. The demonstration provides an early proof point that production support of HMC will be delivered with Altera’s Generation 10 portfolio — includes both Stratix 10 and Arria 10 FPGAs and SoCs.
Altera now offers a fully verified EtherCAT (Ethernet for Control Automation Technology) protocol intellectual property (IP) for Altera FPGAs. With the offering, engineers can leverage the performance and integrate a discrete EtherCAT device in an existing FPGA with confidence and minimum effort.
Altera launched their Generation 10 FPGA and SoC devices. The Generation 10 devices will help engineers to develop highly customized solutions that increases system performance and system integration while lowering operating expenses. Initial samples of Arria 10 devices will be available in early 2014. Altera will have 14nm Stratix 10 FPGA test chips in 2013 and Quartus II software support for Stratix 10 FPGAs and SoCs in 2014.
Altera introduced a direct memory access (DMA) reference design. The solution is constructed for Stratix V customers needing to seamlessly and quickly design PCIe Gen3 solutions. Stratix V GX FPGAs feature a hardened protocol stack for PCIe Gen3 applications, demanding the highest in bandwidth, system integration and flexibility, at a reduced cost with lower total power consumption. The new DMA reference design makes it fast and easy to develop high-performance PCIe Gen3x8 hardware.
Altera has released a SDK for OpenCL and supported third-party production boards. The SDK for OpenCL enables software programmers to access the high-performance capabilities of programmable logic devices. The Altera SDK for OpenCL is currently available for download. The annual software subscription for the SDK for OpenCL is $995 for a node-locked PC license.
Microsemi will host a webinar on single event upset (SEU). Attendees will learn about the risks and consequences of configuration failures in Flash, Antifuse and SRAM FPGA technologies, as well as background information on the physical failure mechanisms associated with SEUs. The webcast is titled SEU Immunity: Is Your Design Really Safe? The online seminar will take place Wednesday, April 17 at 8 am PDT.
Xilinx has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs. The company’s goal is to fill in the growing gaps in ASIC and ASSP offerings for next-generation smarter networks and data centers.
Lattice Semiconductor introduced the latest versions of Lattice Diamond and iCEcube2 design tools. The new versions improve power calculations and design productivity for the creation of mobile and consumer, communication, and industrial systems that undergo fast design cycles, demand power efficiency, and have aggressive cost constraints.