Tag Archives: Encoder

Barco Silex Debuts Multi-channel Video over IP with JPEG 2000 Reference Design

Barco Silex multi-channel Video over IP with JPEG 2000 reference design

Barco Silex released the multi-channel Video over IP with JPEG 2000 reference design. The VoIP reference design integrates the BarcoSilex JPEG 2000 Encoder and Decoder IP Cores, the Barco Silex high-performance memory controller core, and the Xilinx SMPTE 2022-1/2 and Ethernet MAC LogiCORE IP Cores for Xilinx 7 Series FPGAs and Zynq All Programmable SoC.

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Vanguard Software Solutions Debuts AVC-I Encoder and Decoder Core for FPGA Devices

Vanguard Software Solutions introduced their AVC-I encoder and decoder core for FPGA devices. A SVC codec core will be available in the fourth quarter. In addition, VSS is also developing a new HEVC FPGA core that will be available next year. The HEVC core will provide customers with access to real-time, HEVC functionality with FPGA flexibility.

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NTT Decoder LSI FPGA for 10-bit 4:2:2 H.264 and MPEG-2

NTT Electronics has developed a FPGA version of a multi-standard single chip LSI for both H.264/AVC 4:2:2 10-bit (including AVC-Intra 100/50) and MPEG-2 4:2:2 decoding. The 1080p 60 FPGA version will be released in the first quarter of 2011. By 2012, NTT Electronics expects to have over 10 models of next-generation H.264/AVC encoder/decoder LSIs.

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Jointwave H.264 Encoder IP Cores

Jointwave introduced their H.264 series encoder IP core. The Jointwave IP cores support Level 1.0 to 5.1 of H.264 (MPEG-4 Part 10, also called AVC). The cores cover baseline profile, main profile, and high 4:2:2/4:4:4 profile. Compare to competitors’ solutions, Jointwave’s IP core uses less hardware resources. The H.264 encoder features ultra-low frequency, super low latency, small die size, and ultra-low power consumption. Jointwave H.264 IP core can be used without embedded or external CPU, and reduce the system complexity. It runs on FPGA and ASIC.

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