Tag Archives: DEBUG

Altera Announces Free Debug and Timing Closure Altera Training Classes

Altera free online technical training courses

Altera is offering several free online technical training courses. The educational classes help designers stay up to date on the latest FPGA products, features, and design techniques. Engineers can learn the recommended debug methodology and analysis techniques and how to use the latest debugging tools. Topics cover include debug, timing analysis and closure.

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Synopsys Debuts Deep Trace Debug for HAPS FPGA-based Prototyping Systems

Synopsys Deep Trace Debug feature for HAPS FPGA-based prototyping systems

Synopsys rolled out a new Deep Trace Debug feature for their HAPS FPGA-based prototyping systems. HAPS Deep Trace Debug increases productivity for debugging complex SoCs by enabling prototypers to capture the long signal trace history needed to identify the root cause of design bugs. HAPS Deep Trace Debug support in Synopsys’ Identify RTL debugger software and HAPS Deep Trace Debug SRAM daughter boards is available now.

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Xilinx Releases ISE Design Suite v13.4

Xilinx rolled out version 13.4 of their ISE Design Suite. ISE Design Suite 13.4 features public access to the MicroBlaze Micro Controller System (MCS), new RX Margin Analysis and debug capabilities for the 28nm 7 Series FPGAs and partial reconfiguration support for the Artix-7 family and Virtex-7 XT devices. ISE Design Suite v13.4 is available now for all ISE Editions. List prices start at $2,995 for the Logic Edition.

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New Certify Multi-FPGA ASIC Prototyping Software and Identify RTL Debugger

Synopsys released the latest version of their Certify multi-FPGA ASIC prototyping software and Identify RTL Debugger. The new release of Identify and Certify FPGA software tools feature an improved flow, which results in higher productivity for users of Synopsys’ HAPS FPGA-based prototyping systems. It also ensure that engineers who build their own hardware prototypes can do so faster and with less effort. The latest release of Identify and Certify FPGA-based prototyping tools are available now.

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White Paper: FPGA-Controlled Test (FCT): What it is and why it is needed

ASSET InterTech published a white paper about a new method for validating, testing and debugging circuit boards by embedding a board-tester-in-a-chip. The title of the technical article is: FPGA-Controlled Test (FCT): What it is and why it is needed. The paper describes a method call FPGA-controlled test (FCT). FCT involves the automatic insertion of multiple embedded instruments into a field programmable gate array to function as a board tester. The embedded board tester is then operated from an intuitive drag-and-drop graphical user interface.

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White Paper: Using Multi-Gigabit Transceivers to Test and Debug FPGA

Byte Paradigm recently published a white paper about testing and debugging a FPGA with multi-gigabit transceiver. The technical paper features Byte Paradigm’s new Thunder Series probe. The PC-based instrument uses FPGA multi-gigabit transceivers as high-speed interface for collecting trace data and inserting test pattern stimulus during FPGA testing and debugging. The article discusses the advantages of using high bandwidth links in combination with adequate embedded instrumentation IP implemented in FPGA.

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SpringSoft ProtoLink Probe Visualizer

SpringSoft announced their ProtoLink Probe Visualizer. The tool increases design visibility and simplifies debugging of FPGA-based prototype boards. ProtoLink Probe Visualizer achieves a high level of design visibility and makes prototype boards easier to debug starting at the early RTL design stage all the way through final implementation. The tool shortens the verification cycle of off-the-shelf or custom-designed prototypes. The ProtoLink Probe Visualizer is available now for a list price of $40,000 (USD) for a one-year subscription license.

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GateRocket to Present FPGA Verification and Debug Solutions

At two EDA industry events, GateRocket will describe best practices for reducing FPGA verification and debug times. The first presentation will take place at the EDA Tech Forum in Westborough, Massachusetts at 12:40 pm (Eastern) on Thursday, October 14, 2010. The second presentation will in the EDA Virtual Summit (as part of verification track) at 4 pm (Eastern) on Thursday, October 14, 2010. Both events are free with advance registration.

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Mentor Graphics, GateRocket FPGA Verification Through Synthesis Flow

GateRocket teamed with Mentor Graphics to streamline the verification-through-synthesis flow for FPGA design. The integrated solution features GateRocket’s tool set for FPGA debug and verification with Mentor’s Precision Synthesis FPGA tool suite, which is a rad-tolerant synthesis-based solution. The Ssynthesis flow enables designers to more efficiently verify and debug high-reliability features such as synthesis-based triple modular redundancy (TMR) and compliance with safety-critical standards such as DO-254.

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Best Tools for Verification and Debug of FPGAs

At ESC Boston, GateRocket will conduct a class, Best Tools for Verification and Debug of FPGAs. The course will be presented by Dave Orecchio, President and CEO of GateRocket, a supplier of FPGA design and debug solutions for Xilinx and Altera programmable devices. The event will take place at 3:15 pm, Wednesday, September 22, 2010 in Room 103, Hynes Convention Center, Boston.

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