Tag Archives: CPLD

Altera Debuts Five New Low Cost Cyclone V FPGA Development Kits

Altera introduced five new low-cost development kits based on its Cyclone V FPGAs. The Altera kits make it easy for designers to cost-effectively get started on FPGA development with an entry point of just $49. Altera’s portfolio of low-cost CPLDs, FPGAs and SoCs are available now in production. All low-cost development kits supporting the portfolio are available today.

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Altera Quartus II Software Version 11.1

Altera rolled out version 11.1 of their Quartus II design software for CPLD, FPGA and HardCopy ASIC designs. Quartus II software version 11.1 includes expanded support for Altera’s 28nm FPGAs, including compilation support for Arria V and Cyclone V FPGAs and enhanced support for Stratix V FPGAs. Both the Subscription Edition and the free Web Edition of Quartus II software version 11.1 are now available for download.

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Altera MAX V CPLD Device Family

Altera launched their new MAX V CPLD device family. The MAX V CPLD devices use half the total power compared to competitive CPLDs. The MAX V CPLD device family includes seven members ranging in density from 40 to 2,210 LEs. The first two MAX V devices, the 5M80ZE64C5N and 5M240ZT100C5N devices, are available now, priced at $1.70 and $4.90, respectively (100-unit quantities). All MAX V family members will be available in full production by the end of the second quarter of 2011.
The MAX V maintains the instant-on, single-chip, non-volatile characteristics of the original MAX series.

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Lattice Semiconductor ispMACH 4000ZE CPLD Family Goes Green

Lattice Semiconductor is offering halogen- and lead-free packages for their ispMACH 4000ZE CPLD family. The green products feature metal oxides or red phosphorous instead of bromine and chlorine, which are halogens associated with ozone depletion. Lead and halogens have been eliminated from several components of the ispMACH 4000ZE IC package material to comply fully with industry standards such as Japan’s JEIDA and Europe’s WEEE. For lead-frame based packages, the plating process has been modified to remove lead, and halogens have been removed from die-attach and mold compounds that encapsulate the IC.

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Lattice ispLEVER Classic 1.4 Design Tool Suite

Lattice Semiconductor launched ispLEVER Classic design tool suite, version 1.4. The upgraded ispLEVER Classic features Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH 4000ZE CPLD fitter with improved power optimization. Classic 1.4 software is compatible with Windows XP/Vista/7 and operates as a 32-bit application. The ispLEVER Classic 1.4 tool suite is available now for free. Designers can also download the optional Synopsys Synplify Pro logic synthesis and Aldec Active-HDL simulator modules.

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Synopsys Synplify and Synplify Pro Synthesis Tools for Lattice

Synopsys and Lattice Semiconductor have agreed to a multi-year extension to their agreement. Under the terms of the OEM agreement, Lattice Semiconductor will provide specific versions of Synopsys’ Synplify Pro and Synplify software as part of its programmable logic design environments (including the Lattice Diamond FPGA design platform). The logic synthesis partnership will benefit designers targeting Lattice CPLD and FPGA products.

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Altera Quartus II Software Version 10.0 for CPLD, FPGA, HardCopy ASIC

Altera announced version 10.0 of their Quartus II development software for CPLD, FPGA and HardCopy ASIC designs. Quartus II software v10.0 features 2X to 3X faster compile times than the nearest competitor for high-density designs. The latest software release includes support for Altera’s 28-nm Stratix V FPGA family and offers several new productivity features that enable design teams to achieve faster timing closure and shorten time to market. Both the Subscription Edition and the free Web Edition of Quartus II software v10.0 are now available for download.

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Altera Quartus II Software Version 9.1

Altera unveiled version 9.1 of their Quartus II software for CPLD, FPGA and HardCopy ASIC designs. Both the Subscription Edition and the free Web Edition of the Quartus II software version 9.1 are currently available for download. Quartus II software subscribers receive the ModelSim Altera Starter Edition and a full license to the IP Base Suite, which includes 14 of Altera’s most popular IP (DSP and memory) cores. The annual software subscription is $2,495 for a node-locked PC license and is available for purchase at Altera’s eStore or from authorized distributors.

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Lattice MachXO Control Development Kit

Lattice Semiconductor introduced the new MachXO Control Development Kit and 12 new reference designs for prototyping system control functions such as temperature and current monitoring, power supply sequencing, fan control and fault logging, that are commonly found in telecom infrastructure, server, industrial and medical applications. The MachXO kit enables the development of system control designs for designers of CPLDs and low-density FPGAs. Promotional pricing for the MachXO Control Development Kit is $119.

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Altera Enhances MAX II CPLD Family

Altera is now offering MAX IIZ CPLDs in industrial-grade temperature ranges and at lower power than before (55% lower static power). The MAX IIZ CPLDs’ combination of density, I/O, and small package size, make them an ideal fit for cost- and power-sensitive applications. These new capabilities open MAX IIZ CPLDs to a broader range of markets such as industrial, computer and office automation, medical, and consumer applications. Altera’s MAX IIZ EPM240Z M68 devices are available now for $1.25 in high volumes. Over 20 MAX IIZ design examples are also available.

More info: Altera MAX IIZ Devices