Altera announced the production availability of their 40-Gbps Ethernet and 100-Gbps Ethernet intellectual property cores. The cores can be used to create high-performance, low-cost, subsystem IP in Stratix IV and Stratix V FPGAs. Altera’s 40GbE and 100GbE IP cores are compatible with the recently announced Quartus II software v12.0. They are available for download on the Altera website.
RF Engines Limited (RFEL) is developing demodulator cores for FPGA devices. Building blocks include many typical demodulation functions such as symbol timing recovery, fine frequency/phase estimation and correction and SNR estimation. RFEL combined these functions to support multiple demodulation schemes simultaneously – providing parallel soft-symbol data stream outputs. RFEL’s demodulator cores will be available for licensing later this year.
Lattice Semiconductor and Helion GmbH teamed on Intellectual Property (IP) cores for the video security and surveillance camera market. Helion’s IONOS video pipeline IP and Vesta evaluation platform targets the LatticeXP2, LatticeECP2M, and LatticeECP3 FPGA families. The Helion Vesta evaluation platform is a completely self-contained platform that enables the development and realization of image pipelines for camera systems, especially in tight form-factor video security applications such as network IP and dome cameras.
The EE Times Virtual Conference titled, Maximizing the Flexibility of FPGAs, will take place Thursday, June 24th from 11:00am to 6:00pm EDT. The virtual conference features speeches, webinars, discussion panels, and live interactive chats on the topic of programmable logic and the design flexibility it allows. The online event will take place on your computer.
Actel introduced intellectual property (IP) cores for SmartFusion intelligent mixed signal FPGAs. A large library of Actel IP cores are included in the Libero Integrated Design Environment (IDE) IP bundle, with obfuscated-RTL version included with the free Libero Gold license, and RTL-source version included with the $2,500 Libero Platinum license. The library of Actel’s IP cores can be configured and connected in the Libero IDE SmartDesign IP design tool.
EnSilica introduced version 2.1 of eSi-RISC Development Suite. It is a platform for evaluating EnSilica’s family of eSi-RISC highly configurable and low-power soft processor cores. eSi-RISC Development Suite v2.1 is a development environment for the creation, implementation and test of eSi-RISC processor embedded application designs. The eSi-RISC family of processors for embedded systems has been extensively silicon proven in a number of ASIC and FPGA technologies.
Altera introduced an industrial safety data package for automation applications. Altera created a pre-qualified development tool chain, including safety manuals and safety intellectual property (IP) cores. The Altera solution will shorten development time and lower total system cost in safety-critical industrial applications, such as servo and inverter drives, safety devices, and automation controllers. Altera’s industrial safety data package will be available early in the second quarter of this year.
EnSilica announced the eSi-1600, eSi-3200, and eSi-3250 highly configurable and low-power soft processor cores. The new processor cores are available immediately for deployment as part of EnSilica’s full specification-to-silicon design service through a number of leading foundries and an FPGA integration service utilizing devices from all the leading vendors.