Tag Archives: CAST

CAST Debuts H.264 Video Over IP – HD Encoder Subsystem

CAST H.264 Video Over IP - HD Encoder Subsystem

CAST announced the H.264 Video Over IP – HD Encoder Subsystem. The reusable subsystem makes it easier to build video streaming into mobile and other products. Reference designs for the streaming subsystem are available now for the Altera Stratix IV and Arria V families, and the Xilinx Kintex-7 line. These include the CAST and other essential IP cores implemented in an FPGA, plus the necessary interfaces, memory, drivers, and software.

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CAST Offers Ultra-low Latency Video Encoding Option for H.264 IP Cores

CAST announced an ultra-low latency video encoding option for their H.264 video encoder IP cores. The new option enables near-real time video transmission for streaming and wireless video applications, especially when coupled with CAST’s hardware stacks for fast, processor-less video processing.

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Beyond Semiconductor, CAST Debut BA25 Advanced Application Processor

BA25 Advanced Application Processor Core ~ Beyond Semiconductor and CAST

Beyond Semiconductor and CAST announced the BA25 Advanced Application Processor. It is the latest member of the BA2x family of 32-bit processor IP cores. The BA25 Advanced Application Processor Core is available now and is already in use by early customers. The IP core is ideal for demanding embedded applications. It is suitable for use as the main processor for systems running general-purpose operating systems like Linux or Android.

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CAST Unveils H.264 High-Profile Video Encoder IP Core for FPGA and ASIC Devices

CAST H264-HP-E H.264 High-Profile Encoder IP Core for FPGAs and ASICs

CAST announced the H264-HP-E video encoder IP core. The ISO/IEC 14496-10 and ITU-T H.264 High Profile specification compliant H264-HP-E video encoder IP core is sourced from Alma Technologies. It is available now and is ideal for HD broadcast, professional video cameras, and video storage. An intra-only version features extremely low latency for real-time applications, and is suitable for AVC-Intra 50 and 100 implementations.

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CAST UDPIP IP Core

CAST introduced the UDPIP IP core. The CAST UDPIP is a hardware implementation of the User Datagram Protocol (UDP), which is a fast, simple, transport layer protocol that works without the handshaking and error correction of the more rigorous Transmission Control Protocol (TCP). The UDPIP IP core is available now in Verilog or as an optimized netlist for Altera and Xilinx FPGAs. Integration with MAC cores from CAST, FPGA vendors, or other sources is available. Integration with CAST compression cores (e.g., the H.264 encoder) is also available.

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Webinar: How to Achieve the Highest NAND Flash Application Data Rate

CAST and Evatronix will host a webinar about using CAST’s new NAND Flash Controller Core as part of an overall design strategy to achieve the highest possible memory data input and output rates for advanced applications. The webcast will take place Wednesday, November 30, 2011 at 1:00 PM EST. The online seminar is free, but you need to register in advance.

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CAST NAND Flash Controller IP Core v6 Supports Latest High-Speed Memory Devices

CAST, Inc. rolled out version six of their NAND Flash Memory Controller IP core. The CAST NANDFLASH-CTRL Core is available in synthesizable RTL for ASICs or optimized netlists for FPGAs. Versions of the royalty-free controller core range from a lean, asynchronous-only core (for long-term or boot-code storage applications) through a full-featured, high-speed core (for applications needing the full bandwidth of the latest memory devices).

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CAST 32-bit BA22 Processor Cores for Embedded Systems

CAST announced their royalty-free BA22 Processor IP Family for ASICs and FPGAs. The new IP cores are based on the BA22 design sourced from Beyond Semiconductor. The BA22 processor cores feature pipelined 32-bit RISC BA22 architecture, caches and memory management units, up to 32 general purpose registers, enhanced arithmetic processing capabilities (divider and floating point units), power-management unit, interactive JTAG-based debug capability, 1.41 DMIPS/MHz, frequencies from 50 MHz to over 300 MHz, 12,000 to 38,000 gates, and require only 0.023 mW/MHz (in a 65nm process).

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PCIEXPAIF Application Interface Core for Altera, Xilinx FPGA PCIe Hard IP

CAST announced their PCIEXPAIF IP Core for integrating PCI Express in an FPGA-based system. The IP core includes a high-level interface between system buses like AMBA AXI4 and the PCI Express hard macro blocks available from Altera and Xilinx. The PCIEXPAIF IP Core integrates a completer controller and DMA controller with up to eight DMA channels. The functionality of the DMA controller can be extended using the Scatter-Gather controller. The CAST core supports 32- and 64-bit versions of the open source Wishbone Bus and the AMBA AHB, AXI and AXI4 buses.

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