Tag Archives: Boundary Scan

eBook: Testing System Clocks with Boundary Scan (JTAG) and an FPGA

Testing System Clocks with Boundary Scan (JTAG) and an FPGA

ASSET InterTech published a new ebook that explains how cost-effective verification of system clocks during prototype circuit board bring-up and manufacturing can be accomplished with several different methods based on JTAG and boundary-scan testing or IP in an FPGA. The title of the ebook is Testing System Clocks with Boundary Scan (JTAG) and an FPGA.

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