Tag Archives: Barco Silex

Barco Silex Debuts Multi-channel Video over IP with JPEG 2000 Reference Design

Barco Silex multi-channel Video over IP with JPEG 2000 reference design

Barco Silex released the multi-channel Video over IP with JPEG 2000 reference design. The VoIP reference design integrates the BarcoSilex JPEG 2000 Encoder and Decoder IP Cores, the Barco Silex high-performance memory controller core, and the Xilinx SMPTE 2022-1/2 and Ethernet MAC LogiCORE IP Cores for Xilinx 7 Series FPGAs and Zynq All Programmable SoC.

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Barco Silex BA411E Universal AES Crypto Engine

Barco Silex introduced BA411E, which is an enhanced version of their multi-purpose AES crypto engine. The BA411E IP core supports multi-pipelined architectures, multiple data path configurations, and a wide range of ciphering modes. With the universal AES crypto engine, S-boxes can be efficiently implement as simple logic for ASIC or as memories for FPGA. The same level of flexibility and performance can be easily obtained on any existing FPGA technology or ASIC process.

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Barco Silex BA414E Public Key Crypto Engine IP Core

Barco Silex announced the BA414E Public Key Crypto Engine Intellectual Property (IP) core. The BA414E is based on a scalable, highly pipelined and optimized arithmetic unit. The BA414E PK Crypto Engine can be mapped to any existing FPGA technology and all ASIC processes with reconfigurable elementary DSP blocks. The BA414E IP does not require any assistance from the main CPU to handle the complete Public Key processing. Based on a cost-effective µ-coded sequencer (coupled to a µ-DMA), the core can support complex operations and algorithms like RSA, CRT, DSA and ECDSA (including pre- and post-processing).

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