Microsemi has achieved National Institute of Standards and Technology (NIST) algorithmic certification on their U.S.-developed EnforcIT Cryptography Suite of National Security Agency (NSA) Suite B algorithms. The EnforcIT Cryptography Suite was validated by InfoGard Laboratories, Inc. and certified by the NIST. The certification is expected to be posted to the NIST website later this month.
Xilinx has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs. The company’s goal is to fill in the growing gaps in ASIC and ASSP offerings for next-generation smarter networks and data centers.
CAST announced the H264-HP-E video encoder IP core. The ISO/IEC 14496-10 and ITU-T H.264 High Profile specification compliant H264-HP-E video encoder IP core is sourced from Alma Technologies. It is available now and is ideal for HD broadcast, professional video cameras, and video storage. An intra-only version features extremely low latency for real-time applications, and is suitable for AVC-Intra 50 and 100 implementations.
Tokyo Electron Device Limited (TED) introduced the TB-7V-2000T-LSI ASIC development test platform. The inrevium TB-7V-2000T-LSI features a Xilinx Virtex-7 FPGA. The TB-7V-2000T-LSI makes it possible to perform emulation and prototyping of large SoCs using a single FPGA instead of the multiple chips required in the past. The TB-7V-2000T-LSI ASIC development test platform can be ordered today. The tool will be begin shipping in early December 2012.
Flexras Technologies launched their Wasga Compiler. The automatic partitioning tool increases multi-FPGA design by a factor of ten. Wasga Compiler complements FPGA-based SoC prototyping. The software tool features high clock frequencies, fast execution time, and unlimited design capacity. It supports multi-billion ASIC gates equivalents designs, and maps them to any Altera or Xilinx board. Wasga Compiler is available now.
Aldec released version 2012.02 of their Riviera-PRO. The latest version of the mixed-language verification tool supports a number of advanced verification methodologies that will benefit the designers of complex FPGAs and those migrating to ASIC. Riviera-PRO v2012.02 supports the verification environments constructed with the Universal Verification Methodology (UVM) class library and new SystemVerilog IEEE 1800-2009 and VHDL IEEE 1076-2008 constructs. This makes Riviera-PRO an ideal platform for working with the Open Source VHDL Verification Methodology (OS-VVM).
Microsemi announced a private labeling program for their SmartFusion customizable system-on-chip (cSoC), and flash and antifuse-based FPGA solutions. Microsemi’s new private label program enables companies to rapidly deliver economical and differentiated system-on-chip solutions. With the company’s SmartFusion cSoC devices, engineers can reduce the size of their circuit boards and the external bill-of-material component count while at the same time increasing the mean time between failure.
Altera rolled out version 11.1 of their Quartus II design software for CPLD, FPGA and HardCopy ASIC designs. Quartus II software version 11.1 includes expanded support for Altera’s 28nm FPGAs, including compilation support for Arria V and Cyclone V FPGAs and enhanced support for Stratix V FPGAs. Both the Subscription Edition and the free Web Edition of Quartus II software version 11.1 are now available for download.
Thanks to expanded support for the Universal Verification Methodology (UVM) with comprehensive transaction-level visual debugging, engineers can now use Riviera-PRO 2011.06 advanced debugging infrastructure without having to manage basic mechanisms for transactions handling. Aldec Riviera-PRO is an ideal verification platform for building up layered, coverage driven, constrained-random environments for functional verification of ASIC and FPGA designs.
Barco Silex introduced BA411E, which is an enhanced version of their multi-purpose AES crypto engine. The BA411E IP core supports multi-pipelined architectures, multiple data path configurations, and a wide range of ciphering modes. With the universal AES crypto engine, S-boxes can be efficiently implement as simple logic for ASIC or as memories for FPGA. The same level of flexibility and performance can be easily obtained on any existing FPGA technology or ASIC process.