Tag Archives: 100G

Stratix V FPGA Powers Altera Multirate OTN 100G Muxponder IP Solution

Altera multi-rate OTN (optical transport network) muxponder solution for 100G network aggregation

Altera introduced a single-chip, multi-rate OTN (optical transport network) muxponder solution for 100G network aggregation. The multi-rate muxponder IP solution is based on Altera’s 28nm Stratix V FPGA devices. The solution enables engineers to customize systems and target FPGA architectures that are optimized for specific design requirements. The multirate 100G muxponder IP solution expands the capabilities of current networks by enabling developers to integrate emerging client types into their networks, such as 16G Fibre Channel.

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Altera Packs Two 100G Transponders on a Single FPGA

Altera created a single-chip, dual 100G transponder solution that is implemented in a 28nm high-performance Stratix V FPGA. With the new dual 100G transponder solution, Altera is now able to deliver density that is unachievable with current solutions and puts them on the path to support data rates of 400G and beyond. Altera is currently shipping 28-nm Stratix V FPGAs and OTN IP.

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White Paper: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs

Altera published a white paper about how Altera FPGA devices are addressing 100-GbE line card design challenges. As various standard bodies finalize the 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want to design 100G production systems. As a result of increasing demand for more bandwidth, service providers are looking at emerging 40-GbE/100-GbE standards for their next-generation line card options. Altera Stratix V FPGAs solve the bandwidth problem by providing integrated 12.5-Gbps transceivers with hardened 100G PCS functions on the 28nm technology node.

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Xilinx Goes Shopping Again, Acquires Sarance Technologies

Xilinx has acquired Sarance Technologies. The acquisition will help Xilinx increase and accelerate the displacement of ASSPs and ASICs in many 40G/100G and beyond programs. Sarance Technologies is a supplier of ASIC and FPGA IP cores for packet processing. The cores include Interlaken IP, classification and traffic management IP.

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Xilinx Acquires Modelware, Debuts 100G Traffic Management Reference Design

Xilinx has acquired Modelware, which is a provider of traffic management/packet processing silicon intellectual property (IP) cores and reference designs that simplify system development and enable greater differentiation for networking applications supporting 10G, 40G, 100G and beyond. Xilinx also announced a FPGA-based 100G traffic management reference design for speeding evaluation and implementation of high bandwidth packet processing applications.

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Altera EFEC7 and EFEC20 100G IP Cores

Altera introduced the EFEC7 and EFEC20 enhanced forward error correction (EFEC) IP cores. The multi-dimensional IP cores are optimized for high performance Stratix IV and Stratix V series FPGA devices. The EFEC7 and EFEC20 were developed by Altera’s Newfoundland Technology Centre (formerly Avalon Microelectronics). They are ideal for 100G applications such as metro and long-haul optical transport networks (OTN). According to Altera, they are the first company to offer an integrated, single source 100G solution.

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Xilinx Virtex-6 HXT FPGA Optical Transport Network Design Platform

Xilinx introduced the Virtex-6 HXT FPGA Optical Transport Network (OTN) Targeted Design Platform. The OTN Targeted Design Platform features a Virtex-6 HXT FPGA development board with pre-defined and implemented reference designs for different OTN solutions, such as 100G ODU switching from Xilinx, 100G Ethernet to OTU4 transponders and 10×10 to OTU4 transponders. The OTN platform also includes a highly optimized IP 100G MuxSAR solution developed by Omiino. The Virtex-6 HXT FPGA OTN Kit will be available in April for $25,000 (without optical modules).

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Vitesse 40G and 100G CI-BCH eFEC for ASIC and FPGA Implementation

Vitesse Semiconductor introduced their patented Continuously Interleaved BCH (CI-BCH) enhanced forward error correction (eFEC) technology for implementation in ASICs or FPGAs. According to Vitesse, their CI-BCH eFEC code offers the highest performing hard decision eFEC available and is the industry’s only eFEC implementable in FPGA form at 100G. Vitesse’s CI-BCH eFEC enables both 40G and 100G backbones to operate over 25% to 50% longer spans, respectively, with low power, low cost, and low latency.

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Altera Stratix IV GT EP4S100G2 FPGA in Volume Production

The Altera Stratix IV GT EP4S100G2 FPGA is now shipping in volume production. The Stratix IV GT EP4S100G2 FPGAs feature integrated 11.3-Gbps transceivers. The EP4S100G2 FPGAs meet the high-speed bandwidth requirements for next-generation framer, MAC, bridging and switching applications for 100-Gigabit Ethernet (GbE), and 100-Gigabit Optical Transport Networks (OTN). Altera’s 100G solutions help communications systems designers developing 100G systems to accelerate their time to market and reduce risk compared to ASICs, ASSPs and other currently available FPGA technologies.

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