The Danish Technological Institute (DTI) selected SystemCrafter to demonstrate the benefits of a SystemC design flow. SystemC and SystemCrafter were incorporated into a design flow from functional specification to implementation. The DTI found that this approach resulted in fast protoyping and verification, reuse of test benches at different design stages and simulation 10-100 times faster than pure RTL. SystemCrafter SC v3 was used in a number of examples to demonstrate the hardware/software codesign workflow, including a second order biquad type IIR filter used for coefficient calculation. This has been implemented and tested on a Xilinx ML405 board with an embedded power PC.
The design flow started with a functional view written in C++, identifying the sub components and interfaces but with no implementation details. The architecture view allocated each subcomponent to a hardware or software implementation. The IIR filter was written in SystemC (system level) and then compiled to a gate level SystemC and corresponding HDL (VHDL) description using SystemCrafter SC v3. It was then possible to simulate the system level and gate level descriptions using the same SystemC test bench. The SystemC simulation times for 1000 samples were <1s at the functional level, 2s for system level and 23s for gate level.
According to a senior consultant at the Danish Technological Institute, embedded software developers can develop FPGA designs with SystemC and SystemCrafter SC with only a little extra learning. Designers could use the same language for both software and hardware development.