Synopsys Synplify r2012.09 Synthesis Tools Reduce FPGA Implementation Time
Synopsys released the newest version of their Synplify Pro and Synplify Premier FPGA synthesis tools. The 2012.09 release of Synplify includes new multiple error isolation and incremental fix capabilities that accelerate FPGA implementation. The features enable FPGA designers and engineers deploying FPGA-based prototypes such as Synopsys’ HAPS systems to speed design project schedules by weeks.
The 2012.09 release of the Synplify Pro and Synplify Premier synthesis software is available now. Customers with a current maintenance agreement can download this new version from Synopsys using their SolvNet account. The Synplify FPGA synthesis products are supported on Windows and Linux, 32 and 64-bit platforms.
The 2012.09 Synplify Premier release offers enhancements for engineers targeting Altera and Xilinx FPGA devices. The release includes support for Achronix Speedster 22i HD FPGAs. Synplify customers with all-vendor configurations of Synplify Pro and Premier can now target Achronix’s Speedster22i HD FPGAs built on Intel’s 22nm process technology with 3-D Tri-Gate transistors.
For engineers targeting Xilinx 7 Series devices, new automated constraints setup assistance and checking for Xilinx’s Vivado Design Suite simplifies migration from the Xilinx ISE design software, saving time and enhancing quality of results.
For designers targeting Altera FPGAs, the new version of the Synplify Premier tool provides high reliability capabilities, such as triple modular redundancy (TMR) and automatic inference of error-correcting code (ECC) memories.
2012.09 Synplify Pro and Synplify Premier Synthesis Software Highlights
- New hierarchical design error isolation and incremental fix capabilities
- Enhanced continue-on-error capability
- Reduces design cycles by speeding up design fixes
- Decreases the number of iterations needed to successfully bring-up the FPGA design on the board
- Can automatically identify and isolate multiple erroneous modules and interface issues in a single synthesis run
- Erroneous modules can now be exported, fixed in parallel with the main design, and then merged back into the design incrementally
- Engineers can create custom reports early in the synthesis run
- TCL script-based searches of the design database to find converted clocks
- Integrated Synopsys and Xilinx RTL-to-gates flow
- Flow simplifies the migration path to the Xilinx Vivado Design Suite for designers using Xilinx 7 Series FPGAs
- Defines a migration path from Xilinx’s ISE place-and-route flows to Vivado flows by providing constraints translation, constraints editing, review and reporting within the Synplify tool
- High-reliability features have been extended to support Altera devices
- Designers can create immunity to radiation effects that cause single event upsets (SEUs)
- Enables the creation of fault-tolerant sequential logic including state machines
- Helps designers to automatically implement error mitigation circuitry including automatically distributed TMR with voting logic
- Automatic inference of Altera error correcting memory primitives
More info: Synopsys FPGA Implementation
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