Synplicity®, Inc. (NASDAQ:SYNP) has added System Designer(tm), a device-independent intellectual property (IP) configuration and system-level assembly environment, to Synplify Pro® and Synplify® Premier FPGA design implementation tools. The System Designer(tm) capability allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then easily implement it into a variety of FPGA vendor devices, including those from Actel, Altera, Lattice Semiconductor, and Xilinx. System Designer is included, at no charge, for Synplify Pro, Synplify Premier and Certify customers on active maintenance as of April 2008. It is available immediately.
System Designer is built on the open source Eclipse, a de facto standard providing for exceptional extensibility. In addition, the System Designer capability allows Synplify Pro and Synplify Premier users to maintain and deploy internally developed system-level building blocks and components which have been converted to the IP-XACT format, and then re-use them across multiple designs and multiple generations of FPGA designs. The new tool flow provides FPGA designers, using IP and system-level blocks, with an extremely productive path to implementing complex systems in FPGAs.
The System Designer tool accepts as input IP, which complies with the SPIRIT Consortium’s IP-XACT standard for describing IP, and outputs top-level RTL and a Synplify project file ready for synthesizing the complete design. Third-party IP is available to System Designer users via web browser access integrated into Synplicity’s synthesis products. Through the Synplify Pro and Synplify Premier FPGA design implementation tools, designers using the System Designer capability can browse and download IP from Synplicity partners participating in the ReadyIP program, currently ARM, CAST, Gaisler Research, Synopsys and Tensilica, and thus easily evaluate various options for their FPGA designs.
System Designer is a key component of Synplicity’s ReadyIP Initiative, a program that takes aim at simplifying the access, evaluation and use of IP for FPGA-based system designs. The ReadyIP program allows users to evaluate and “try-before-they-buy” IP within their designs through System Designer using Synplicity’s industry-leading synthesis tools.
More info: Synplicity