Lattice ispLEVER Classic 1.4 Design Tool Suite

Lattice Semiconductor launched ispLEVER Classic design tool suite, version 1.4. The upgraded ispLEVER Classic features Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH 4000ZE CPLD fitter with improved power optimization. Classic 1.4 software is compatible with Windows XP/Vista/7 and operates as a 32-bit application. The ispLEVER Classic 1.4 tool suite is available now for free. Designers can also download the optional Synopsys Synplify Pro logic synthesis and Aldec Active-HDL simulator modules.

Lattice ispLEVER Classic 1.4 Highlights

  • Minimizes the dynamic power consumption of ispMACH 4000ZE CPLDs
  • Fitter automatically enables the device’s Power Guard feature for unused I/O and clock resources to avoid unnecessary internal switching
  • Improved features and educational material for the ispMACH 4000 CPLD family
  • Synthesis interface includes additional optimization control and a means to reference a Synplify Design Constraints (SDC) file for timing objectives
  • ispLEVER Classic software Online Help has been expanded to make designing with Lattice CPLDs even easier and more efficient
  • New generic schematic library manual describes logic symbols that are portable across SPLD and CPLD device families
  • Classic 1.4 design software is bundled with the ispVM System 17.8 programming environment

Synplify Pro HDL Analyst provides designers a way to rapidly visualize high-level register transfer level (RTL) Verilog or VHDL. Engineers can cross-probe between the graphical diagrams and source code to ensure that the coding style they use is the most efficient for the target CPLD. Finite State Machines (FSM), for example, are popular functions designed into CPLDs. FSMs are automatically extracted by HDL Analyst and displayed graphically as a bubble diagram with state transition arrows and a table of state encodings.

More information: Lattice Semiconductor ispLEVER Classic Software