Synplicity (NASDAQ: SYNP) and Xilinx (NASDAQ: XLNX) have agreed to extend their Ultra High-Capacity Joint Task Force activities to address area utilization and lowering power consumption. For over a year, both companies have worked closely to define and implement new solutions to maximize the quality of results and productivity for ultra high-density designs implemented in Xilinx 65-nm Virtex(TM)-5 FPGAs. The first deliverable of the Synplicity-Xilinx joint task force was the development of SmartCompile(TM) Technology, an incremental design flow that improves run times by up to 6X while maintaining exact design preservation of unchanged logic. This RTL to place-and-route flow supports incremental changes so designers who need to make small modifications to an FPGA don’t have to recompile the entire device.
The initial phase of the Ultra High-Capacity Joint Task Force focused on providing dramatic improvements in overall quality of results and run time and ensuring the stability of results when incremental changes are made to an FPGA design. Phase II of the task force takes this progress to the next step â€” area reduction and lowering power consumption at 65-nm and below.
The overall goal of the joint task force is to provide designers with near push-button results for ultra high-density designs along with the ability to complete multiple design iterations per day. In view of the wide variety of applications enabled by ultra high-capacity FPGAs, the joint task force will deliver multiple design flows and tools optimized to meet the unique design requirements of these devices.