Synopsys released the latest version of their Certify multi-FPGA ASIC prototyping software and Identify RTL Debugger. The new release of Identify and Certify FPGA software tools feature an improved flow, which results in higher productivity for users of Synopsys’ HAPS FPGA-based prototyping systems. It also ensure that engineers who build their own hardware prototypes can do so faster and with less effort. The latest release of Identify and Certify FPGA-based prototyping tools are available now.
Certify can now produce up to 30% faster FPGA-to-FPGA transmission performance using High-Speed Time Domain Multiplexing (HSTDM). This results in a higher overall performance of designs prototyped with HAPS. Both software tools also feature incremental compilation technology that accelerates implementation of design revisions, and automation to ease the partitioning of large designs into multiple HAPS boards. The new Certify and Identify software tools are designed for use with Synopsys’ HAPS systems. However, enhancements in the FPGA tools also benefit custom and build-your-own prototypers.
Certify Multi-FPGA ASIC Prototyping Software Highlights
- Increases data throughput of prototypes enabled by up to 30% faster HSTDM of I/Os
- Quickly brings up prototypes built with multiple HAPS boards using system target Tcl scripting
- Produces very accurate static timing analysis estimates with post-route delay back annotation
- Speeds ASIC design migration with support for encrypted DesignWare Library IP
- Obtains a more complete resource analysis of multi-FPGA designs with new PCB trace impact analysis
Identify RTL Debugger Highlights
- New and enhanced capabilities that improve debug throughout the design cycle and reduce turnaround time
- Debugger results annotated in the RTL View of the Synplify HDL Analyst graphical analysis tool
- Isolates defects by tracing longer periods of signal activity with up to 64 times more sample buffer capacity Update
- Implements design instrumentation faster with Synplify compile point technology by preserving design modules not affected by debug instrumentation