Oregano IEEE-1588 IP Cores for LatticeECP3, LatticeECP2M FPGA Devices

Lattice Semiconductor and Oregano Systems introduced IEEE-1588 Timing Node System IP cores for the LatticeECP3 and LatticeECP2M FPGA families. The SoC-class IP cores are syn1588 Clock_S, syn1588 Clock_M, and syn1588 VIP. The syn1588 VIP is a single chip IEEE 1588 solution. The syn1588 Clock_S IP core offers the full syn1588 technology with a minimum amount of resources required. The syn1588 Clock_M IP core offers the full syn1588 technology with support for trigger and IO events. The Oregano clock cores are compatible to the IEEE1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems.

IEEE 1588 Syn1588 Clock_S Core

Oregano IEEE 1588 Syn1588 Clock_S IP Core
  • Supports 10/100 Mbit/s half and full duplex modes
  • Delivered with PTP Version 1.0 and version 2.0 stack (Linux or Windows)
  • Supports SPI cascade and independent slave mode
  • SPI data rates up to 20 Mbit/sec
  • 16-bit SPI data transfers, 32 bit interface to the internal SPI controller
  • 1 pps output
  • 1 period timer output with a period ranging from 14,000 sec down to 200ns
  • 1 event input which draws a time stamp and stores it in the time stamp FIFO
  • Events may be processed at a burst rate of 1 MHz
  • 1 trigger output signal which may be used to generate a signal transition at a given point in time
  • All event, period, and trigger signals are strictly synchronous to the internal high accuracy clock
  • Delivered with test bench, 100% code coverage guaranteed
  • Optional support of GPS timing receivers
  • RMII Interface option available upon request

IEEE 1588 Syn1588 Clock_M Core

Oregano IEEE 1588 Syn1588 Clock_M IP Core
  • Supports 10/100 Mbit/s half and full duplex modes
  • Delivered with PTP Version 1.0 and version 2.0 stack (Linux or Windows)
  • Supports SPI cascade and independent slave mode
  • SPI data rates up to 20 Mbit/sec
  • 16-bit SPI data transfers, 32 bit interface to the internal SPI controller
  • 1 pps output
  • 2 period timer output with a period ranging from 14,000 sec down to 100ns
  • 2 event input which draws a time stamp and stores it in the time stamp FIFO
  • Events may be processed at a burst rate of 5 MHz, dependent on host processor speed
  • 2 trigger output signal which may be used to generate a signal transition at a given point in time
  • All event, period, and trigger signals are strictly synchronous to the internal high accuracy clock
  • Delivered with test bench, 100% code coverage guaranteed
  • Optional support of GPS timing receivers
  • RMII Interface option available upon request

IEEE 1588 syn1588 Versatile IP

Oregano IEEE 1588 syn1588 Versatile IP (VIP)
  • 10/100/1000 Mbps Ethernet MAC included, compliant to IEEE802.3-2000
  • IEEE1588-2008 hardware time stamping
  • IEEE1588 hardware clock
  • IEEE1588-2008 Layer 2 compliant
  • 1-step and 2-step master
  • IEEE1588-2008 Layer 3 compliant (UDP, ARP, DHCP)
  • Clock accuracy better than 50ns
  • syn1588 PTP stack running on integrated 8-bit CPU core
  • 1 pps output
  • Arbitrary frequency output
  • Event input
  • Node remotely controlled via IEEE1588 management messages (in layer 3 mode)
  • Direct replacement for GPS receiver
  • Grand Master operation with seamless link to external GPS timing receiver
  • Analog PLL using an external TCVCXO or OCVCXO
  • Default, telecom and power profile supported
  • Multicast and unicast PTP message supported

More info: Oregano Systems – Design & Consulting | Lattice Semiconductor