PARS Features MathWorks Simulink HDL Coder Support

Sundance DSP recently announced that its PARS development tool now supports The MathWorks Simulink HDL Coder. PARS is designed to target parallel systems comprising DSPs and FPGAs. PARS is a MATLAB / Simulink toolbox that can also generate Hardware-In-the-Loop applications (HIL) for real-time testing on a multiprocessor system. Target platform applications can communicate with host side applications being run under Simulink and exchange data back and forth through host interfaces. Price of PARS is 10K US dollars for a single user seat and does not require run-time licensing. Site licenses are also available.

PARS is an established tool for developing a multi-DSP/FPGA application from a single Simulink model and is being used by industry leaders such as the US Navy, General Motors, Oak Ridge National Laboratory, and Rockwell Collins for developing leading-edge applications. Engineers who use Simulink to create models and Simulink HDL Coder to automatically generate hardware implementation code can now focus on their application and let PARS automatically generate the code for the FPGAs and DSPs in their system. With the help of The MathWorks Real-Time Workshop, PARS generates a single application from a single Simulink model, which will contain the entire code of the DSPs, and FPGAs in the system including all the communication with built-in synchronization between Host processor, DSPs and FPGAs.

Programming of multi FPGA systems has traditionally been complex and time consuming, requiring deep knowledge of both parallel processing and FPGA programming techniques. This has been an adoption barrier for scientists and system level engineers who could use heterogeneous parallel systems with many processing elements with the power of multi FPGA and DSP platforms for their applications.

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