Dune Networks and MorethanIP announced the availability of SPAUI and RXAUI intellectual property (IP) cores for FPGAs and ASICs. MorethanIP’s SPAUI and RXAUI are optimized for Altera’s Stratix II GX, Stratix IV, and Xilinx Virtex 5 LXT / FXT devices to provide a solution for storage, telecommunications, and data center applications. The identical cores can also be targeted seamlessly to ASIC and Structured ASIC, providing a low-risk path to cheaper devices. The new cores are available now from MorethanIP. Pricing for the SPAUI MAC core starts at US $25,000 for an FPGA encrypted, configurable-code version.
MorethanIP’s offering of SPAUI and RXAUI IP cores include a configurable SPAUI MAC, a programmable four-Lane PCS (Physical Coding Sub-layer) and a programmable two-Lane XAUI PCS (also known as RXAUI). The configurable MAC core implements the SPAUI functions, such as CRC check and calculation, BCT (Burst Control Tag) to support channelization and burst interleaving traffic, Preamble and IPG (Inter-Packet Gap) compression with out-of-band, in-band with the LLFC (Link-Level Flow Control) bit, packet agnostic and standard IEEE flow-control schemes. The SPAUI MAC core also includes a FIFO interface to simplify system design and integration of third-party cores and customer applications.
The PCS core’s interface embedded SERDES operates at rates of up to 6.5Gbps per lane in existing FPGA devices or ASIC technologies. The PCS cores implement the line coding, channel bonding functions.
MorethanIP’s offering of SPAUI and RXAUI IP cores was tested and validated with Dune’s new generation of FAP devices, called the PETRA family, which includes the P220, P230, and P130 devices. The PETRA device family offers highly integrated 40G and 80G Traffic Manager and Fabric devices, integrating up to eight SPAUI and RXAUI interfaces, as well as standard XAUI and SGMII interfaces.
The new IP cores are delivered with the MorethanIP user-friendly configuration graphical user interface, through which designers can easily eliminate features that are not required, reducing unit costs and simplifying software integration. MorethanIP supplies the SPAUI cores with the ability to do functional simulation using an industry standard VHDL or Verilog simulator or synthesis tool, as well as place-and-route and static timing analysis using FPGA and ASIC design tools.