Altera to Make Five Presentations at DesignCon

Altera will be attending DesignCon, February 4-5, at the Santa Clara Convention Center. Altera will make five presentations:

  • Design/Verification for High-Speed I/Os at Multiple to >10 Gbps
  • FPGA/ASIC Pre-Driver PDN SSN and Its Impact on SSJ
  • Incorporating SSN Analysis in Constraint-Based System Design
  • A New Physical Mechanism-Based Jitter Classification Method
  • Continuous PLL Adaptation to Variable Reference Input Frequency

Design/Verification for High-Speed I/Os at Multiple to >10 Gbps
Review the latest design/verification developments, plus architecture, circuit, and process technology advancements for high-speed links emphasizing jitter and signal integrity for FPGAs with ~10 Gbps I/Os.
Monday, Feb. 2, 1:30-4:30 pm

FPGA/ASIC Pre-Driver PDN SSN and Its Impact on SSJ
An overview of SSN behavior of FPGA/ASIC pre-driver PDN excited by different SSO signal patterns and the physics behind PDN resonance will be explored.
Tuesday, Feb. 3, 8:30-9:10 am

Incorporating SSN Analysis in Constraint-Based System Design
Higher interface bandwidths have increased FPGA pin counts and signaling rates have increased higher SSN. A SSN – aware methodology for defining/optimizing PCB design rules that ensure system reliability will be presented.
Tuesday, Feb. 3, 9:20-10:00 am

A New Physical Mechanism-Based Jitter Classification Method
A new jitter-classification method based on physical mechanisms rather than distribution function will be discussed. The physical properties and associated distribution models will be examined plus an overview of a mapping function to unify both methods.
Tuesday, Feb. 3, 11:05-11:45 am

Continuous PLL Adaptation to Variable Reference Input Frequency
PLLs are configured to operate with one known input frequency and generate an output clock signal by multiplying or dividing the input, but if the input frequency is unknown, the PLL is still required to operate correctly. This innovative apparatus assists PLLs to adapt to any input frequency and generate a pre-determined output frequency.
Wednesday, Feb. 4, 11:05-11:45 am

More info: Altera