Under the newly ratified JESD79-3 JEDEC DDR3 SDRAM Standard, Altera’s (NASDAQ: ALTR) Stratix(R) III family of FPGAs provides designers with the high-performance and low-power benefits of DDR3 memory that are becoming increasingly critical for a wide range of communications, computing and video processing applications.
Stratix III FPGAs support read and write leveling functionality embedded directly into the I/O element. This helps ensure compliance with the JEDEC write leveling requirement and corrects alignment of data reaching the FPGA fabric. DDR3 DRAM makers Elpida, Micron, Qimonda, Samsung and Hynix have all qualified various speed and density DDR3 memory devices for subsequent end-product use.
The fly-by termination used in DDR3 improves signal integrity, but causes flight time skew between the clock and data signals. Altera’s implementation compensates for the skew by providing staggered DQ signals for high-speed operation.
DDR3 memory meets the low-power and high-performance requirements of today’s advanced memory applications. Stratix III FPGAs offer support for the DDR3 SDRAM high-speed external memory interface on up to 1,104 user I/O pins arranged in 24 modular I/O banks with dedicated DQS logic on all I/O banks and 31 embedded registers per I/O for maximum DDR3 performance. Stratix III devices support DDR3 with a maximum clock speed of 400 MHz and maximum data rate of 800 Mbps.