FPGA Blog - field programmable gate array and structured asic

Altera 28nm Stratix V FPGA Family

Altera introduced the 28nm Stratix V FPGA family. The Stratix V FPGA family features up to 1.6 Tbps of serial switching capability; up to 1.1 million logic elements (LEs); 53-Mbits embedded memory; 3,680 18×18 multipliers; and integrated transceivers operating up to 28 Gbps. Samples of Stratix V FPGAs are expected in the first quarter of 2011.

Altera Stratix V FPGA Variants

• Stratix V GT FPGA
  Industry’s only FPGA with integrated 28-Gbps transceivers targeting 100G systems and beyond
• Stratix V GX FPGA
  Supports a wide range of applications with 600-Mbps to 12.5-Gbps transceivers
• Stratix V GS FPGA
  Optimized for high-performance digital signal processing (DSP) applications with 600-Mbps to 12.5-Gbps transceivers
• Stratix V E FPGA
  Highest density FPGA ideal for ASIC prototyping, emulation or high-performance computing applications

Stratix V FPGA Architecture Enhancements

• New adaptive logic module (ALM) architecture
  adds up to 800K additional registers in the largest device to maximize logic efficiency. The ALM architecture is ideal for heavily pipelined and register-rich designs
• Enhanced embedded memory structure featuring M20K blocks
  Offers improved area efficiency and higher performance
• Industry’s first variable-precision DSP block
  Provides the highest efficiency and performance across multiple-precision DSP data paths
• User friendly partial reconfiguration
  Allows designers to reconfigure part of the FPGA while other sections remain running

More info: Altera

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