Altera Stratix IV FPGA Webcasts

This week, Altera launched three new webcasts on the new 40-nm Stratix IV FPGA product line. The three webinars are: (1) Introducing Altera’s 40-nm Portfolio, (2) Reach New Levels of SoC Integration with 40-nm FPGAs, and (3) Minimize SSN and Jitter with Advanced Transceiver Technology.

Introducing Altera’s 40-nm Portfolio
Challenges for today’s high-end digital systems include increasing performance, reducing power consumption, and increasing system bandwidth and integration. Overcome all of these challenges with Altera’s new 40-nm portfolio, which includes Stratix® IV FPGAs, HardCopy® IV ASICs, Quartus® II software version 8.0, and supporting intellectual property (IP). You will learn:

  • How this 40-nm portfolio addresses system integration, power consumption, and system bandwidth issues
  • How Altera’s partnership with its foundry, TSMC, provides the lowest-risk path to cutting-edge technology
  • How Altera’s FPGA software improves the power and performance of your system
  • How only Altera can provide the benefits of FPGAs AND the benefits of ASICs

Reach New Levels of SoC Integration with 40-nm FPGAs
FPGAs are an ideal platform for system-on-a-chip (SoC) integration due to their inherent flexibility and time-to-market advantages. Altera’s 40-nm custom logic portfolio, which includes the new Stratix® IV FPGAs and HardCopy® IV ASICs, offers benefits in terms of density, performance, features, and interface bandwidth for new levels of system-on-a-chip integration. In this webcast you will learn:

  • The three most important high-end digital system requirements
  • About the optimal mix of interface bandwidth and core performance
  • How transceiver quality affects your system bandwidth
  • How to achieve power efficiency with high-end FPGAs
  • How Altera’s system solutions, tools, and intellectual property (IP) enable productivity

Minimize SSN and Jitter with Advanced Transceiver Technology
As data rates and the number of transceiver channels in advanced FPGAs increase, it’s increasingly important that the FPGA is designed to properly isolate analog and digital sources. This webcast presents available architectural advantages, and describes how those advantages minimize the effects of simultaneous switching noise (SSN) and jitter. View the webcast to learn:

  • The basics of SSN and jitter
  • The relationship between SSN and jitter, and how one affects the other
  • How advanced transceiver architectures can minimize SSN and jitter