DINI Group DN7006K10PCIe 8T ASIC Prototyping Engine

The DN7006K10PCIe, from The DINI Group, features Altera Stratix III FPGAs. The high-density board supports six 3SL340′s in 1760-pin packages to provide 1,120 I/O’s per chip. Chip to chip communication is 600 MHz (1.2 Gb/s) LVDS. The board offers ASIC prototype developers the fastest possible implementation. The DN7006K10PCIe will be supplied with 1 to 6 FPGAs in various sizes and speed ranges with prices for fully configured boards starting at less than $10k.

DINI Group DN7006K10PCIe-8T ASIC Prototyping Engine

The board is hosted in an 8-lane PCIe slot (controller included) or used stand-alone and configured with USB, CompactFLASH, or JTAG. On-board global clock networks (7) and DDR2 SODIMMS (4) provide the user with speed and flexibility. The DN7006K10PCIe enbables ASIC and FPGA designers to prototype logic designs and run them at near real time clock speeds in multiple FPGAs.

Reference designs, diagnostics, and models for partitioning are included. They are available “off-the-shelf” directly from The DINI Group and its agents.

DN7006k10PCIe-8T Features

  • PCI Express (8-lane) logic prototyping system with 2-6 Altera Stratix3 FPGA’s
  • Fixed 8-lane PCIe interface and controller provided
  • Easy PCIe core prototyping with our exclusive PCIe PIPE Slowdown Core
  • 15+ million ASIC gates (ASIC measure) when stuffed with 6 Stratix3 3SL340′s
  • FPGA to FPGA interconnect is a mix of single-ended or LVDS
  • Main Bus(MB) connects all Stratix3 FPGA’s (96 signals)
  • Auspy models for partitioning assistance
  • 4 separate DDR2 SODIMMs (250MHz)
  • SODIMM Daughtercard expansion
  • Seven independent low-skew global clock networks
  • Flexible customization via daughter cards
  • Fast and Painless FPGA configuration
  • RS232 port for embedded uP debug
  • Full support for embedded logic analyzers via JTAG interface
  • 54 status FPGA-controller LED’s: enough illumination to decontaminate minimally processed vegetables

More info: DN7006K10PCIe-8T FPGA Prototyping Engine (pdf)