Synopsys, Altera and TSMC teamed together to create silicon-accurate modeling of key parasitic effects in Synopsys’ StarRC solution for TSMC’s 28 nanometer (nm) processes. Altera has successfully deployed StarRC to achieve signoff accurate extraction and accelerate the design cycle of its 28nm FPGA designs. StarRC is now fully deployed as the signoff parasitic extraction solution for 28-nanometer Stratix V FPGA devices.
The StarRC solution achieved the stringent model-to-silicon accuracy criteria of TSMC’s 28-nm process technology to enable high-performance designs at the advanced node. With the solution, engineers can realize the benefits of the Synopsys, Altera and TSMC collaboration and deploy the solution to achieve a high standard of accuracy on leading-edge 28-nanometer designs.
At advanced nodes (28-nm and below), process modeling complexity has increased significantly due to continued transistor scaling, the increasing number of metal and dielectric layers, new device structures and the increased field effects between devices and interconnects. Several second-order effects that could be ignored in the past must now be accurately modeled and extracted to ensure desired circuit behavior. StarRC offers silicon-accurate modeling for the new 28-nm process effects as validated by foundries and customers on their taped-out designs.
StarRC Key 28nm Features
- Modeling of increased conductor width variation due to advanced retargeting and optical proximity correction (OPC) effects
- Via-faceting and coupling effects of larger via shapes
- Area-dependent via resistance and capacitance
- Enhanced layout-dependent device parasitic extraction
- Rapid3D field solver technology for fast, high-accuracy 3D extraction that is also qualified by TSMC for the 28-nm node