Aldec introduced ALINT 2010.02 for design rule checking. Altera and Xilinx FPGA vendor primitives are now supported to enable accurate design rule checking on the latest FPGA devices. ALINT 2010.02 is available now. The tool offers support for RMM, STARC, DO-254 and Aldec design rule plug-ins, which are sold separately.
The 2010.02 release of ALINT includes support for Reuse Methodology Manual (RMM) design rules that define a methodology for efficient reuse and verification of System-On-A-Chip (SoC) designs.
Aldec ALINT Features
- Fast design analysis of complex ASIC/FPGA/SOC designs
- IEEE VHDL, Verilog and mixed-language designs
- STARC VHDL or Verilog rule plug-ins
- DO-254/ED-80 VHDL or Verilog rule plug-ins
- RMM rule plug-in
- Custom rule creation
- Integrated result analysis and debugging environment
ALINT is Design Rule Checking software for fast design closure. The software analyzes and detects issues early in the design and verification cycle of complex ASIC, FPGA and SoC designs. The latest release includes advanced technology enabling detection of all the levels of RTL design issues – starting from comparatively simple naming conventions and design structure to advanced topics such as reuse, optimal synthesis, power and area consumption, Design-For-Test (DFT), and Clock Domain Crossings (CDC).
More info: Aldec