Synopsys rolled out a new Deep Trace Debug feature for their HAPS FPGA-based prototyping systems. HAPS Deep Trace Debug increases productivity for debugging complex SoCs by enabling prototypers to capture the long signal trace history needed to identify the root cause of design bugs. HAPS Deep Trace Debug support in Synopsys’ Identify RTL debugger software and HAPS Deep Trace Debug SRAM daughter boards is available now.
The new Deep Trace Debug feature improves state machine coverage, prototyping coverage, and test pattern generation. It offers about 100 times more signal storage capacity than the traditional memory storage employed by on-chip FPGA logic debuggers. HAPS Deep Trace Debug enhances both capacity and fault isolation capabilities while freeing up the on-chip FPGA memory required for validating complex system-on-chip (SoC) designs.
By pairing a HAPS Deep Trace Debug SRAM daughter board with the Synopsys Identify Intelligent Integrated Circuit Emulator (IICE), HAPS Deep Trace Debug enables many unique signal probes with complex triggers to be recorded and provides deeper memory to store extensive state history as the system executes. The SRAM daughter board also frees up the FPGA’s on-chip RAM for prototyping an SoC design’s memory blocks. Normally, engineers have had to make a choice between capturing long signal trace histories that consume extensive FPGA memory resources or saving FPGA memory resources but losing detailed visibility into signal trace history.
HAPS Deep Trace Debug Features
- Combination of new Synopsys HAPS hardware and Identify software enables greater visibility of internal signals in FPGA-based prototypes to accelerate SoC design debug
- Provides approximately 100X more storage capacity for signal traces with sample speeds up to 60 MHz
- Utilization of FPGA memory resources significantly reduced to better accommodate complex SoC prototyping projects
More info: Synopsys, Inc.