Microsemi Debuts SmartFusion2 System-on-Chip Field Programmable Gate Arrays

Microsemi SmartFusion2 system-on-chip field programmable gate array

Microsemi introduced the SmartFusion2 system-on-chip field programmable gate array family. The device features flash-based FPGA fabric, a 166 megahertz (MHz) ARM Cortex-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM and high-performance communication interfaces. The SmartFusion2 SoC FPGA is ideal for safety-critical applications in industrial, defense, aviation, communications and medical applications. The SmartFusion2 M2S050T samples are available now. First production silicon is expected in early 2013.

Microsemi SmartFusion2 SoC FPGA

SmartFusion2 features a physically unclonable function (PUF) key enrollment and regeneration capability. In addition, SmartFusion2 is the only SoC FPGA protected from differential power analysis (DPA) attacks using technology from the Cryptographic Research Incorporated (CRI) portfolio. As a result, engineers can leverage built-in cryptographic processing accelerators including: advanced encryption standard (AES) AES-256, secure hash algorithm (SHA) SHA-256, 384-bit elliptical curve cryptographic (ECC) engine and a non-deterministic random bit generator (NRBG).

Microsemi Smartfusion2 FPGA devices are designed to meet industry standards like IEC 61508, DO254 and DO178B, and feature SEU immunity of zero failures in time (FIT). In addition, SmartFusion2 flash FPGA fabric does not require external configuration, which provides an added level of security since the SoC FPGA retains its configuration when powered off and enables device “instant-on” performance.

SmartFusion2 is the only SoC FPGA that protects all its SoC embedded SRAM memories from SEU errors. This is accomplished through the use of single error correction, double error detection (SECDED) protection on embedded memories such as the Cortex-M3 embedded scratch pad memory, Ethernet, CAN and USB buffers, and is optional on the DDR memory controllers.

Microsemi SmartFusion2 SoC FPGAs offer designers 100x lower standby power compared to equivalent SRAM-based FPGAs without sacrificing performance. The Flash*Freeze standby power mode can be initiated with a simple command. In this mode all registers and SRAM retain state, I/O state can be set, the microprocessor sub-system (MSS) can be operational while low frequency clock and I/Os associated with MSS peripherals can be operational. The device can enter and exit Flash*Freeze mode in approximately 100 micro seconds.

SmartFusion2 devices are available with a range of density from 5K LUT to 120K LUT plus embedded memory and multiple accumulate blocks for digital signal processing (DSP). High bandwidth interfaces include PCI Express (PCIe) with flexible 5G SERDES along with high-speed double data rate DDR2/DDR3 memory controllers. The device also includes a microprocessor sub-system (MSS) with a 166 MHz ARM Cortex-M3 processor, on chip 64KB eSRAM and 512KB eNVM to minimize total system cost. The MSS is enhanced with an embedded trace macrocell (ETM), 8 Kbyte instruction cache, and peripherals including controller area network (CAN), Gigabit Ethernet and high speed USB 2.0. Optional security accelerators can be used for data security applications.

Microsemi SmartFusion2 SoC FPGA Features

  • 120K LUT, 5Mbit SRAM, 4Mbit eNVM
  • Integrated DSP processing blocks
  • 166MHz ARM Cortex-M3 with on chip eSRAM and eNVM
  • ETM and Instruction Cache
  • Extensive peripherals CAN, TSE, USB
  • 16x 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES
  • Hard 800 mbps DDR2/3 controllers with SECDED (EDAC) protection
  • Built in design security on all devices without manufacturing overhead
  • Protection against tampering, cloning, overbuilding, reverse engineering and counterfeiting
  • Supply-chain assurance with digital Certificate of Conformance
  • DPA Hardened, AES256, SHA256, Random Number Generator
  • 384 bit Elliptical Curve Cryptographic (ECC) Engine, Pseudo-PUF challenge-response service
  • SEU Immune Zero FIT Flash FPGA Configuration Cells
  • SEU Protected Memories: eSRAMs, DDR Bridges (MSS, MDDR, FDDR), Instruction Cache, Ethernet, CAN and USB Buffers, PCIe, MMUARTand SPI FIFOs
  • Hard 800 mbps DDR2/3 controllers with SECDED (aka ECC or EDAC) protection
  • Design digest capability
  • Industry’s lowest static power 10mW during operation on the 50K LUT device
  • 1mW standby power in Flash*Freeze real time low power state
  • Simple command to initiate Flash*Freeze mode
  • Retains all register and SRAM state in Flash*Freeze mode
  • MSS can be operational during Flash*Freeze with low frequency clock
  • System Builder for creation of system level architecture
  • Synthesis, debug and DSP support from Synopsys
  • Simulation from Mentor Graphics
  • Push button design flow with power analysis, and timing analysis
  • SmartDebug for access to non-invasive probes within SmartFusion2 devices
  • Integrated firmware flows for GNU, IAR and Keil

More info: Microsemi SmartFusion2 SoC FPGA (pdf)