Xilinx Virtex-5 IBIS-AMI FPGA Transceiver Models

Xilinx released IBIS-AMI models for FPGA transceivers. The Xilinx IBIS-AMI models enable designers to reduce simulation time from hours to minutes. HSPICE simulations of 100Gbps designs can take hours to achieve a result. With IBIS-AMI models, engineers in the FPGA industry will see 100x faster simulation times. Xilinx is the first FPGA provider to release IBIS-AMI models for transceiver technology.

Using Xilinx’s IBIS-AMI models and SiSoft’s Quantum Channel Designer software, systems designers can experiment with different combinations of channel lengths, connectors, via designs and transmit / receive equalization to quickly determine which configurations provide adequate operating margin and which don’t. Pre- and post-layout simulation with Quantum Channel Designer allows designers to validate designs and reduce time to market while increasing confidence in their design’s reliability and manufacturability.

The IBIS-AMI (I/O Buffer Information Specification – Algorithmic Modeling Interface) modeling specification enables standardized, interoperable simulation of SerDes PHYs at the high levels of simulation performance and accuracy needed to correctly predict the behavior of serial links.

Next generation communications, networking, and consumer electronics products are replacing high-speed parallel interfaces with multi-gigabit serial links as the primary means of moving data within a system. Conventional signal integrity and timing analysis (e.g. HSPICE) won’t work for these links, which require analyzing millions of bits worth of behavior to reliably determine how jitter, noise and crosstalk affect link operating margins.

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