Microsemi will host a webinar on single event upset (SEU). Attendees will learn about the risks and consequences of configuration failures in Flash, Antifuse and SRAM FPGA technologies, as well as background information on the physical failure mechanisms associated with SEUs. The webcast is titled SEU Immunity: Is Your Design Really Safe? The online seminar will take place Wednesday, April 17 at 8 am PDT.
The Microsemi webinar will discuss all major FPGA programming technologies (Flash, Antifuse, and SRAM). The webcast is ideal for engineers focused on safety-critical aviation, defense, industrial and medical applications.
SEU Immunity Webinar Topics
- SEU Overview — what they are and why they matter
- Comparison of Flash, Antifuse and SRAM FPGAs and the risks of malfunction due to SEUs
- Results of SEU tests on Flash, Antifuse, and SRAM FPGAs
Single Event Upsets (SEUs)
SEUs are caused when sub-atomic particles such as neutrons strike the silicon substrate of an integrated circuit and cause binary code bits to flip, which can corrupt configuration cells in SRAM FPGAs and may cause catastrophic hardware malfunctions. Free neutrons are present at all levels in the atmosphere, at higher concentrations at higher altitudes, and are especially problematic at aviation altitudes. Sources of sub-atomic particles also exist in IC packaging materials. Microsemi’s Antifuse and Flash-based FPGAs do not experience changes of configuration due to subatomic particles. This is in direct contrast to SRAM FPGAs, which can experience catastrophic changes of functionality due to SEUs affecting their configuration.