ispLEVER 7.1 is the latest FPGA design software from Lattice Semiconductor Corporation (NASDAQ: LSCC). The new tool release delivers a number of new functional and performance-enhancing features, including the industry’s first dedicated FPGA Simultaneous Switching Output (SSO) Analyzer. The SSO Analyzer enables FPGA designers to actively analyze and optimize I/O pin placement and output switching characteristics to minimize undesirable noise and ground bounce on a printed circuit board. To enable designers to achieve higher levels of productivity, the ispLEVER 7.1 design tools also deliver up to 30% faster FPGA design compile times and now support multi-processor powered design compilation to achieve the fastest timing closure.
Lattice’s ispLEVER 7.1 for Windows, Linux and UNIX users is available immediately without charge for customers with active design tool maintenance. The full ispLEVER design tool suite starts at a price of $895 for the Windows version.
An enhanced Power Calculator enables FPGA designers to analyze and optimize power requirements early in their design. The Lattice Power Calculator includes an exceptionally user-friendly interface that enables power analysis at the block level and examination of “what-if” scenarios by changing design environment variables.
The ispLEVER 7.1 release marks a new standard in performance, encompassing improvements in post-route design operating frequency of up to 5% and runtime reductions by as much as 30% for larger designs. These improvements decrease costs, speed-timing closure and help users deliver the best solutions more quickly.
ispLEVER 7.1 now includes Synplify Pro for Lattice. This addition to ispLEVER includes a range of tools and features that help manage large designs, and extract the very best fit and performance, optimized for Lattice FPGAs.
ispLEVER 7.1 also now includes Aldec Active-HDL Lattice Edition (LE), which is a comprehensive and feature-rich simulation environment.
ispLEVER 7.1 New Features
- Windows Vista O/S Support
- “Find Module” Function in Project Navigator
- Interactive Synthesis Flow
- Design Planner Enhancements
- SSO Analyzer
- Interactive Trace Report
- Find and String Filters
- Enhanced EBR and DSP Block Information
- Color Coded Port Groups and DQS Span
- Improved Pin Display Select Dialog
- Preprocessor Directives for Design Preference Files
- Map Place and Route (MPAR) Enhancements
- Multi-core Processor Support for Batch Runs of Place and Route
- Congestion Driven Routing Options
- Guided MPAR
- Reveal(tm) Logic Debugger Tool – Expanded VHDL Support
- Boolean / Integer
- Enumerated Data Types
- Power Calculator Enhancements
- Effective Thermal Resistance
- Power Graph
More info: Lattice Semiconductor ispLEVER