2010.09 Synplify Pro and Synplify Premier FPGA Synthesis Tools

Synopsys introduced the 2010.09 release of Synplify Pro and Synplify Premier FPGA synthesis tools. Synplify 2010.09 products reduce logic synthesis runtimes and enable faster post-netlist incremental design turns. The Synplify Pro and Synplify Premier 2010.09 tools now offer synthesis support for the SiliconBlue iCE65 FPGA family. The tools feature 4X synthesis runtime improvement, global placer, concurrent design development for teams, and support for DesignWare Library datapath and building block components for FPGA Implementation and ASIC Prototyping. Synplify Pro and Synplify Premier 2010.09 are available now. The 2010.09 Synplify FPGA synthesis tools are supported on Windows and Linux, 32 and 64-bit platforms.

2010.09 Synplify FPGA Synthesis Tools Highlights

  • Up to 4X Synthesis Runtime Improvement
    Synplify Premier’s FAST logic synthesis mode now offers up to a 4X speed improvement over traditional logic synthesis when using a single processor. The new compile-point technology enables additional speed improvements with automatic parallel timing-driven synthesis execution on different portions of a design to take advantage of computers with multiple processor cores.

  • Physical Synthesis with New Global Placer for Incremental Quality of Results Improvements
    A new physical synthesis flow within Synplify Premier employs Synopsys’ global placer technology to apply performance improvements to an existing placed and routed design. Physical constraints are automatically determined from prior place and route runs. This makes the flow easy to use for logic synthesis users by freeing them from the need to perform complex physical constraint setup.

  • Team-Design Interface and Bottom-Up Flows allow Parallel Development
    Both the Synplify Premier and Synplify Pro tools incorporate new team-design features for hierarchical project management and concurrent development. Design blocks, or previously verified design IP, can be created and shared internally. Floorplanning is not required, making this flow easy to use. Teams can now manage and review their design implementation results and synthesis settings for each block hierarchically. Design team members can take a snapshot of a block and transfer the design files to the team leader for overall integration into the design. Design blocks can be integrated at both the RTL or EDIF levels, saving time, locking in performance and ensuring predictable results.

  • Comprehensive DesignWare Library Support for FPGA-based Prototyping
    Synplify Premier now supports the full suite of datapath and building block components within DesignWare Library. Synplify Premier users can now synthesize ASIC RTL that instantiates any of the DesignWare Library’s components to create FPGA-based prototypes of their ASIC design and achieve performance-optimized results. ASIC and FPGA component support are now synchronized to help ensure the same DesignWare Library component used in the prototype is also used in the ASIC.

More information: Synopsys