Multi-Gigabit Design with Xilinx IBIS-AMI Models Webinar

Xilinx and Signal Integrity Software (SiSoft) will hold a free webinar on Thursday, November 12th at 10:00 AM PST (11 AM Mountain / Noon Central / 1 PM Eastern). The webcast will outline the advantages of using IBIS-AMI models for transceiver simulation. The IBIS-AMI (I/O Buffer Information Specification – Algorithmic Modeling Interface) modeling specification enables standardized, interoperable simulation of SerDes PHYs at the high levels of simulation performance and accuracy needed to correctly predict the behavior of serial links. The webinar highlights how IBIS-AMI based simulation will increase design reliability while reducing engineering design time.

IBIS-AMI Models Webinar Topics

  • Xilinx IBIS-AMI simulation models for Virtex-5, Virtex-6 and Spartan-6 FPGAs
  • Predicting serial link operating margins using simulation
  • Co-optimizing your channel design and SerDes configuration
  • Assessing the impact of jitter, noise and crosstalk
  • Xilinx IBIS-AMI Design Kits for SiSoft’s Quantum Channel Designer

Next generation communications, networking, and consumer electronics products are replacing high-speed parallel interfaces with multi-gigabit serial links as the primary means of moving data within a system. Conventional signal integrity and timing analysis won’t work for these links, which require analyzing millions of bits worth of behavior to reliably determine how jitter, noise and crosstalk affect link operating margins. The IBIS-AMI modeling specification enables standardized, interoperable simulation of SerDes PHYs at the high levels of simulation performance and accuracy needed to correctly predict the behavior of serial links. This webinar highlights how IBIS-AMI based simulation will enable you to increase design reliability while reducing engineering design time.

Using SiSoft’s Quantum Channel Designer software and IBIS-AMI models, systems designers can experiment with different combinations of channel lengths, connectors, via designs and Transmit / Receive equalization to quickly determine which configurations provide adequate operating margin and which don’t. Pre- and post-layout simulation with Quantum Channel Designer allows designers to validate designs and reduce time to market while increasing confidence in their design’s reliability and manufacturability.

Serial Link Analysis Webinar – Multi-Gigabit Design with Xilinx IBIS-AMI Models