Lattice SFI5 IP Core for LatticeSC/M FPGA Families
The 40 Gbps SERDES Framer Interface, Level 5 (SFI5) Intellectual Property (IP) Core is now available for the LatticeSC and LatticeSCM (collectively, “LatticeSC/M”) FPGA families. The solution features 17 SERializer/DESerializer (SERDES) channels in the LatticeSC/M devices, including the Lattice SFI5 soft IP core, and enables flexible and high performance next generation 40 Gbps systems. The IP core and reference design are provided to customers at no charge. An evaluation copy of the bundle is available now and can be downloaded by registered Lattice design tool users with current maintenance agreements without charge.
Lattice SFI5 IP Core Features
- Full compliance to the Optical Internetworking Forum (OIF) Implementation Agreement OIF-SFI5-01.02
- Data path uses 17 SERDES transceivers operating in 8-bit only mode
- Sixteen 16-bit wide internal receive and transmit data paths
- Supported through the ispLEVER IPexpress tool for easy user configuration and parameterization
- Reference design suitable for use on the Lattice Semiconductor SFI5 Evaluation Board with SERDES channels running at 2.5 Gbps
- Reference design uses the Reveal Logic Analyzer to observe circuit operation
- User-settable parameters to select the allowed number of framing errors for the deskew channel framer to go into or out of locked state
More info: Lattice IP Cores and Reference Designs
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