Xilinx at SEE Symposium, Embedded Systems Conference, and NAB

Xilinx, Inc. (Nasdaq: XLNX) will be attending the 2008 Single Event Effects Symposium (SEE: April 15-17 in Long Beach, California), Embedded Systems Conference (ESC: April 15-17 in San Jose, California), and National Association of Broadcasters Conference (NAB: April 14-17 in Las Vegas, Nevada).

SEE Technical Papers

  • Test Techniques and Lessons Learned: The XRTC Virtex-4 FPGA SEE Test Campaign
  • An Automated Approach to Estimating Hardness Assurance Issues in Triple-Modular Redundancy Circuits in Xilinx FPGAs
  • Upset Test Methodology and Results for a Mitigated-by-TMR MicroBlaze Soft-Core Processor
  • Optimized Virtex-4 FPGA Self Hosting Configuration Management

ESC Hands-On Workshops

  • Build Linux OS Applications with the MicroBlaze Processor
    In this workshop, designers can learn how to build a customized embedded Linux operating system application using the Xilinx(R) MicroBlaze(TM) processor on a low-cost Spartan-3 FPGA to create a flexible, custom microcontroller design with Ethernet interface and configure, build and boot Linux on the board. Tuesday, April 15, 9 a.m., 12:30 p.m., 2:30 p.m., 4:30 p.m.
  • Advances in PowerPC Processor Embedded Development on Virtex FPGAs
    An overview of Virtex-5 FXT FPGA enhanced PowerPC(R) 440 processor system architecture, performance advantages, co-processor acceleration, and Xilinx solutions for system implementation and debug. Using Xilinx tools, designers will learn how to implement a PowerPC processor system and software application utilizing a coprocessor accelerator. Wednesday, April 16, 10 a.m., 12 p.m., 2 p.m., 4 p.m.
  • Building Flexible Signal Processing Applications with XtremeDSP Solutions
    Designers can learn more about high-level design techniques for building video applications using the new XtremeDSP solution Video Starter Kit — Spartan-3A DSP FPGA Edition. Designers will leave the workshop understanding how to use System Generator for DSP to build a video processing pipeline and then connect to the MicroBlaze processor using Platform Studio.

ESC In-Booth Theater Presentations

  • “Introducing the Virtex-5 FXT Platform with Integrated PowerPC 440 Processor”
  • “Advances in PowerPC Processor Embedded Development on Virtex FPGAs”
  • “Linux OS Applications with the MicroBlaze Processor”
  • “Developing Video Applications on Spartan-3A DSP FPGAs”

ESC Product Demonstrations

  • Virtex-5 FXT Platform with Integrated PowerPC 440 Processor — The Ultimate System Integration Platform
  • Low-Cost Embedded Linux Solutions with the MicroBlaze Processor
  • XtremeDSP Solutions — Leading the way in High Performance, Configurable Signal Processing
  • Award Winning Design Tools — Introducing the ISE(R) Design Suite 10.1

ESC Technical Conference Papers

  • Innovations in Configurable Embedded Processing System Architectures
    • J1 Convention Center: ESC 222, Dan Isaacs, Tuesday, April 15, 8:30 a.m.-10 a.m., Xilinx
  • Optimizing Embedded Linux Using HW/SW Co-Design
    • Marriot Salon 5 & 6: ESC 431, Thursday, April 17, 10:30 a.m. – 12 p.m., Xilinx
  • Intro to CPLD & FPGA Design
    • J1 Convention Center: ESC 242 Pt 1, Tuesday, April 15, 12:30 p.m. – 2 p.m., Avnet
    • J1 Convention Center: ESC 262 Pt 2, Tuesday, April 15, 2:30 p.m. – 4 p.m., Avnet
  • Implementing Processors & DSP Functionality within FPGAs
    • J1 Convention Center: ESC 305 Pt 1, Wednesday, April 16, 8:30 a.m. – 10 a.m., Avnet
    • J1 Convention Center: ESC 325 Pt 2, Wednesday, April 16, 10:30 a.m. – 12 p.m., Avnet

Xilinx NAB Demonstrations

  • Triple-Rate SDI Connectivity
    Xilinx will demonstrate new triple-rate SDI reference designs supporting SD-SDI, HD-SDI and 3G-SDI on a single RocketIO(TM) pin. These designs are available free of charge in VHDL or Verilog source code to broadcast equipment manufacturers, enabling them to get to market quickly and easily adapt to 1080p60 standards as they become more broadly adopted. Also available are a wide range of new designs supporting SDI, HD-SDI, Dual Link HD-SDI, 3G-SDI Levels A & B, DVB-ASI, as well as conversion between standards. On the audio side, Xilinx offers reference designs for sample rate conversion at less than 130dB, AES interfaces, and new designs for embedding and de-embedding audio from HD-SDI streams. All of these enable the system architect to concentrate on the value-add portion of their design to deliver the features and benefits for end products that offer better differentiation.
  • Video over IP
    Xilinx will demonstrate broadcast-quality video over IP connectivity by converting an ASI input to a gigabit Ethernet IP output with a Virtex-5 FPGA on the Xilinx ML505 development platform. A second ML505 development platform bridges from an IP input to ASI output. Each bridge is able to achieve full gigabit bandwidth on the IP link and handle up to eight channels of ASI. Packet recovery is demonstrated with the SMPTE 2002 (ProMPEG CoP3) FEC-compliant circuitry. This platform highlights a low risk and scalable FPGA solution for easily incorporating video over IP interfaces.
  • H.264 Main / High Profile Encoding and Decoding
    4i2i will demonstrate live encoding and decoding using the latest release H.264 encoder and decoder IP running on a single Virtex(R)-5 device. 4i2i’s H.264 decoder is designed to be a fully functional high profile decoder in a cost-effective, single-chip implementation. The decoder core is a fully pipelined dedicated video decompression engine that is fully H.264 high profile standard compliant. 4i2i’s IP portfolio has extended over time, keeping pace with video standards and the increased demands of the broadcast industry and now represents a scalable range of applications spanning baseline to high profile.
  • MPEG-2 4:2:2 Profile High-level Encoding and Decoding
    4i2i will also demonstrate the latest MPEG-2 encoder and decoder running on a single Virtex-5. 4i2i offers users the ability to scale their designs across a range of applications from main profile to 4:2:2 profile at high level within the same family of MPEG 2 codecs. 4i2i’s family of encoders are designed to deliver the highest possible video quality in cost-effective, single-chip implementations.
  • HD H.264 Main Profile Encoder
    ATEME and Xilinx will demonstrate a PMC- based multi-channel SD or single-channel HD H.264 encoder platform using Virtex-5 FPGAs. ATEME’s encoder technology, combined with industry-leading Virtex-5 FPGAs, provides unmatched processing power and flexibility, enabling optimal compression efficiency and the best video quality for the most demanding broadcast applications.
  • Advanced Video Development Platform (AVDP)
    Demonstration of PCI Express- compliant cards based on Xilinx Virtex-5 LXT and SXT FPGAs. Developed by OmniTek, the platform enables a standard PC to support professional broadcast quality video processing, capable of streaming uncompressed video to and from the PC via 3G-SDI, Dual Link HD-SDI, HD-SDI, SDI and DVB-ASI connectivity. The AVDP includes free source code IP for scaling, de-interlacing and combining video channels, as well as optimized and flexible interfaces to the embedded PCI Express core in the FPGA and high-speed external memory. The platform offers a quick, low-risk route from prototyping to production for any broadcast system design.
  • JPEG2000 HD and DCI Codecs
    Barco’s new JPEG2000 encoder IP will be featured running on the AVDP. This demonstration will show compression of digital cinema and HD broadcast quality images using a single Virtex-5 FPGA on the AVDP and decompression using a single Virtex-4 FPGA on the Xilinx ML410 development platform. The JPEG2000 IP cores offer significant cost, performance and security advantages over typical codec ASSPs.
  • JPEG2000 HD and DCI Codecs
    intoPIX will feature its new JPEG2000 encoder IP running on the AVDP. This demonstration will show compression of 2K and 4K images using a single Virtex-5 FPGA and decompression through the intoPIX decoder evaluation platform using a single Virtex-4 FPGA. Along with encryption and watermarking IP, the intoPIX JPEG2000 cores offer cost savings, higher performance and more security compared to ASSP-based designs.

More info: ESC | SEE | NAB