Aldec Incorporated released HES(tm) (Hardware Emulation System) 2008.03. The latest release of HES expands the functionality of commercial prototyping boards from The DINI Group and Synopsys®/Synplicity® HAPS(tm) to enable RTL simulation acceleration and emulation on ASIC designs up to 31 million gates. Both design and verification engineers can now benefit from verifying ASIC designs in the hardware, earlier in the design cycle, without the need of buying additional acceleration or emulation systems. HES is available today.
HES automatically partitions an ASIC design across the total available FPGA resource on the multi-FPGA prototyping board. For better flexibility a mix of automated and manual partitioning is available. The limitation of cross-chip connections that often makes a challenge in ASIC prototyping is removed by using automatic signal multiplexing integrated with design partitioning, all with no intervention from a user. The patented ASIC clock conversion algorithm that HES software performs on the post synthesis netlist assures correct porting of ASIC clock tree to the FPGA.
Accellera standard SCE-MI 2.0 interface is now supported in HES 2008.03. The SCE-MI standard defines co-emulation interfaces between the hardware emulator and software testing environment (software application, test bench or an IP). SCE-MI interface ensures portability and reusability of the software and hardware test units across multiple emulation platforms and different vendors. Transaction-based interface reduces the data traffic between the software and the hardware parts of the emulator resulting in significantly increased performance when compared to signal-level interfaces. HES automates the insertion of SCE-MI transactors into the user’s design and provides SCE-MI API functions to interface the transactor from the software side.
More info: Aldec Emulation