Sarance Technologies introduced the HSEC (High Speed Ethernet Core). The HSEC IP is available as soft core for Virtex-5 TXT FPGAs and Altera Stratix IV GT and Altera Stratix IV GX FPGAs, as well as for ASIC implementations. It has also been implemented and validated in 65nm and 40nm process technologies. The IP is delivered as a netlist targeted for the specific FPGA architecture, or as RTL code that can be implemented in any ASIC process technology.
The HSEC IP is the first commercially Media Access Controller (MAC), Physical Coding Sublayer (PCS), and Multi Lane Distribution (MLD) IP conforming to the emerging 40Gigabit Ethernet (40GE) and 100Gigabit Ethernet (100GE) standard. The HSEC IP conforms to Draft 2.0 of the IEEE802.3ba standard and has been tested by major networking and service provider vendors in system laboratories and validated in field trials running over a trillion of error free Ethernet frames over a live 100GE network. The HSEC IP has also been proven to interoperate with a major test equipment vendor.
More info: Sarance Technologies